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EP2058850
European procedure
Extract from the Register of European Patents
EP About this file: EP2058850
| EP2058850 - Semiconductor substrate jig and method of manufacturing a semiconductor device [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 25.03.2011 Database last updated on 25.09.2024 | Most recent event Tooltip | 25.03.2011 | No opposition filed within time limit | published on 27.04.2011 [2011/17] | Applicant(s) | For all designated states Fujitsu Microelectronics Limited 7-1, Nishi-Shinjuku 2-chome Shinjuku-ku Tokyo 163-0722 / JP | [2009/20] | Inventor(s) | 01 /
Teshirogi, Kazuo c/o FUJITSU LIMITED 1-1, Kamikodanaka 4-chome Nakahara-ku, Kawasaki-shi Kanagawa 211-8588 / JP | 02 /
Shimobeppu, Yuzo c/o FUJITSU LIMITED 1-1 Kamikodanaka 4-chome Nakahara-ku, Kawasaki-shi Kanagawa 211-8588 / JP | 03 /
Yoshimoto, Kazuhiro c/o FUJITSU LIMITED 1-1 Kamikodanaka 4-chome Nakahara-ku, Kawasaki-shi Kanagawa 211-8588 / JP | 04 /
Watanabe, Mitsuhisa c/o FUJITSU LIMITED 1-1 Kamikodanaka 4-chome Nakahara-ku, Kawasaki-shi Kanagawa 211-8588 / JP | 05 /
Shinjo, Yoshiaki c/o FUJITSU LIMITED 1-1 Kamikodanaka 4-chome Nakahara-ku, Kawasaki-shi Kanagawa 211-8588 / JP | 06 /
Yoshida, Eiji c/o FUJITSU LIMITED 1-1 Kamikodanaka 4-chome Nakahara-ku, Kawasaki-shi Kanagawa 211-8588 / JP | 07 /
Hayasaka, Noboru c/o FUJITSU LIMITED 1-1 Kamikodanaka 4-chome Nakahara-ku, Kawasaki-shi Kanagawa 211-8588 / JP | [2009/20] | Representative(s) | Fenlon, Christine Lesley Haseltine Lake LLP Lincoln House, 5th Floor 300 High Holborn London WC1V 7JH / GB | [N/P] |
| Former [2009/20] | Fenlon, Christine Lesley Haseltine Lake Lincoln House 300 High Holborn London WC1V 7JH / GB | Application number, filing date | 09151138.6 | 21.03.2002 | [2009/20] | Priority number, date | JP20010322811 | 19.10.2001 Original published format: JP 2001322811 | [2009/20] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP2058850 | Date: | 13.05.2009 | Language: | EN | [2009/20] | Type: | A3 Search report | No.: | EP2058850 | Date: | 03.06.2009 | [2009/23] | Type: | B1 Patent specification | No.: | EP2058850 | Date: | 19.05.2010 | Language: | EN | [2010/20] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 06.05.2009 | Classification | IPC: | H01L21/68 | [2009/23] | CPC: |
H01L21/67092 (EP,US);
H01L21/68 (KR);
B24B37/042 (EP,US);
B32B37/003 (EP,US);
B32B37/1018 (EP,US);
B32B38/0012 (EP,US);
H01L21/67132 (EP,US);
H01L21/6836 (EP,US);
H01L21/6838 (EP,US);
H01L24/27 (EP,US);
H01L24/29 (EP,US);
H01L24/83 (EP,US);
B32B2310/0831 (EP,US);
B32B2457/14 (EP,US);
H01L21/304 (EP,US);
H01L21/78 (EP,US);
H01L2221/68318 (EP,US);
H01L2221/68327 (EP,US);
H01L2221/6834 (EP,US);
H01L2224/83191 (EP,US);
H01L2224/8385 (EP,US);
H01L2924/01004 (EP,US);
H01L2924/01005 (EP,US);
H01L2924/01006 (EP,US);
H01L2924/01013 (EP,US);
H01L2924/01019 (EP,US);
H01L2924/01029 (EP,US);
H01L2924/01033 (EP,US);
H01L2924/01074 (EP,US);
H01L2924/01075 (EP,US);
H01L2924/01082 (EP,US);
H01L2924/01087 (EP,US);
H01L2924/07802 (EP,US);
| C-Set: |
H01L2924/3512, H01L2924/00 (EP,US)
|
| Former IPC [2009/20] | H01L21/67 | Designated contracting states | DE, FR, GB [2009/20] | Title | German: | Halbleitersubstratvorrichtung und Verfahren zur Herstellung einer Halbleitervorrichtung | [2009/20] | English: | Semiconductor substrate jig and method of manufacturing a semiconductor device | [2009/20] | French: | Gabarit de substrat à semi-conducteurs et procédé de fabrication de dispositif à semi-conducteurs | [2009/20] | Examination procedure | 17.08.2009 | Examination requested [2009/40] | 09.11.2009 | Communication of intention to grant the patent | 03.03.2010 | Fee for grant paid | 03.03.2010 | Fee for publishing/printing paid | Parent application(s) Tooltip | EP02252039.9 / EP1304728 | Opposition(s) | 22.02.2011 | No opposition filed within time limit [2011/17] | Fees paid | Renewal fee | 18.05.2009 | Renewal fee patent year 03 | 18.05.2009 | Renewal fee patent year 04 | 18.05.2009 | Renewal fee patent year 05 | 18.05.2009 | Renewal fee patent year 06 | 18.05.2009 | Renewal fee patent year 07 | 30.03.2009 | Renewal fee patent year 08 | 29.03.2010 | Renewal fee patent year 09 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [E]EP1304728 (FUJITSU LTD [JP]) [E] 1-3 * paragraph [0113] - paragraph [0118]; figures 9a-9c *; | [A]US5288663 (UEKI TETSURO [JP]) [A] 1-3 * column 3, line 16 - line 28; figures 9a-9c * | by applicant | JP2001322811 |