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EP2141741
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EP About this file: EP2141741
| EP2141741 - Electronic circuit comprising a diode connected MOS transistor with enhanced efficiency [Right-click to bookmark this link] | Status | The application has been withdrawn Status updated on 05.06.2015 Database last updated on 25.09.2024 | Most recent event Tooltip | 05.06.2015 | Withdrawal of application | published on 08.07.2015 [2015/28] | Applicant(s) | For all designated states STMicroelectronics (Rousset) SAS ZI de Peynier Rousset Avenue Coq 13790 Rousset / FR | For all designated states Université de Provence (Aix-Marseille 1) 3, Place Victor Hugo 13331 Marseille Cedex 3 / FR | [2010/01] | Inventor(s) | 01 /
Battista, Marc 147, Chemin Notre Dame de la Consolation La Bastide 13013 Marseille / FR | 02 /
Chalopin, Hervé Impasse du Château Les Passons 13400 Aubagne / FR | 03 /
Barthelemy, Hervé 17, Rue Sandin 83100 Toulon / FR | [2010/01] | Representative(s) | de Beaumont, Michel Cabinet Beaumont 1, rue Champollion 38000 Grenoble / FR | [N/P] |
| Former [2010/01] | de Beaumont, Michel Cabinet Beaumont 1, rue Champollion 38000 Grenoble / FR | Application number, filing date | 09164596.0 | 03.07.2009 | [2010/01] | Priority number, date | FR20080054555 | 04.07.2008 Original published format: FR 0854555 | [2010/01] | Filing language | FR | Procedural language | FR | Publication | Type: | A2 Application without search report | No.: | EP2141741 | Date: | 06.01.2010 | Language: | FR | [2010/01] | Type: | A3 Search report | No.: | EP2141741 | Date: | 15.08.2012 | Language: | FR | [2012/33] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 16.07.2012 | Classification | IPC: | H01L27/08, H01L21/761, H01L29/861, H01L29/78, H02M7/217, H02M3/07 | [2012/33] | CPC: |
H01L27/0811 (EP,US);
H01L29/783 (EP,US);
H01L29/861 (EP,US);
H02M3/07 (EP,US);
H01L27/0727 (EP,US)
|
| Former IPC [2010/01] | H01L27/07, H01L21/761, H01L29/861, H01L29/78, H02M7/217 | Designated contracting states | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR [2010/01] | Extension states | AL | Not yet paid | BA | Not yet paid | RS | Not yet paid | Title | German: | Elektronischer Schaltkreis mit einem MOS-Transistor in Diodenschaltung mit verbessertem Wirkungsgrad | [2010/01] | English: | Electronic circuit comprising a diode connected MOS transistor with enhanced efficiency | [2010/01] | French: | Circuit électronique comprenant un transistor MOS monté en diode à rendement amélioré | [2010/01] | Examination procedure | 20.12.2012 | Amendment by applicant (claims and/or description) | 20.12.2012 | Examination requested [2013/07] | 05.02.2013 | Despatch of a communication from the examining division (Time limit: M06) | 02.08.2013 | Reply to a communication from the examining division | 07.04.2014 | Despatch of a communication from the examining division (Time limit: M04) | 21.07.2014 | Reply to a communication from the examining division | 15.09.2014 | Despatch of a communication from the examining division (Time limit: M04) | 08.01.2015 | Reply to a communication from the examining division | 29.05.2015 | Application withdrawn by applicant [2015/28] | 29.05.2015 | Cancellation of oral proceeding that was planned for 17.11.2015 | 17.11.2015 | Date of oral proceedings (cancelled) | Divisional application(s) | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 05.02.2013 | Fees paid | Renewal fee | 29.07.2011 | Renewal fee patent year 03 | 24.07.2012 | Renewal fee patent year 04 | 24.07.2013 | Renewal fee patent year 05 | 23.07.2014 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [XY]US6285240 (SHIAU TZING-HUEI [TW], et al) [X] 1,5,6 * column 3, line 11 - line 22; figure 2 * * column 5, line 17 - line 20 * [Y] 3; | [XYI]WO02095835 (VRAM TECHNOLOGIES LLC [US], et al) [X] 1,2,4 * page 16, line 1 - line 5; figures 1-3 * * page 18, line 21 - line 30 * [Y] 3 [I] 7-9; | [XI]EP1855315 (HITACHI LTD [JP]) [X] 1,4,5,7 * paragraphs [0005] , [0033]; figures 1,8,9 * [I] 8,9; | [A] - HOROWITZ P, HILL W, THE ART OF ELECTRONICS, Second Edition, CAMBRIDGE, CAMBRIDGE UNIVERSITY PRESS, (1989), XP002512308 [A] 7-9 * pages 46-48; figures 1.78,1.79A * * page 355 - page 359; figure 6.39B * |