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Extract from the Register of European Patents

EP About this file: EP2346069

EP2346069 - ABRASIVE, POLISHING METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  24.05.2013
Database last updated on 14.11.2024
Most recent event   Tooltip24.05.2013Application deemed to be withdrawnpublished on 26.06.2013  [2013/26]
Applicant(s)For all designated states
Asahi Glass Company, Limited
Shin-Marunouchi Building
1-5-1 Marunouchi
Chiyoda-ku
Tokyo 100-8405 / JP
[2011/43]
Former [2011/29]For all designated states
Asahi Glass Company Limited
12-1, Yurakucho 1-chome Chiyoda-ku
Tokyo 100-8405 / JP
Inventor(s)01 / SUZUKI Masaru
c/o Asahi Glass Company Limited. 12-1, Yurakucho 1-chome Chiyoda-ku
Tokyo 100-8405 / JP
02 / NAKAZAWA Norihito
c/o Asahi Glass Company Limited. 12-1, Yurakucho 1-chome Chiyoda-ku
Tokyo 100-8405 / JP
 [2011/29]
Representative(s)Hock, Joachim
Müller-Boré & Partner
Patentanwälte PartG mbB
Grafinger Strasse 2
81671 München / DE
[N/P]
Former [2011/29]Hock, Joachim
Müller-Boré & Partner Grafinger Strasse 2
D-81671 München / DE
Application number, filing date09824690.307.10.2009
[2011/29]
WO2009JP67519
Priority number, dateJP2008028636607.11.2008         Original published format: JP 2008286366
[2011/29]
Filing languageJA
Procedural languageEN
PublicationType: A1 Application with search report
No.:WO2010052990
Date:14.05.2010
Language:JA
[2010/19]
Type: A1 Application with search report 
No.:EP2346069
Date:20.07.2011
Language:EN
[2011/29]
Search report(s)International search report - published on:JP14.05.2010
(Supplementary) European search report - dispatched on:EP16.05.2012
ClassificationIPC:H01L21/321, C09G1/02, C09K3/14
[2012/24]
CPC:
H01L21/3212 (EP,US); H01L21/304 (KR); B24B37/00 (KR);
C09G1/02 (EP,US); C09K3/14 (KR); C09K3/1463 (EP,US)
Former IPC [2011/29]H01L21/304, B24B37/00, C09K3/14
Designated contracting statesAT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   SE,   SI,   SK,   SM,   TR [2011/29]
TitleGerman:SCHLEIFMITTEL, POLIERVERFAHREN UND VERFAHREN ZUR HERSTELLUNG EINER INTEGRIERTEN HALBLEITERSCHALTUNG[2011/29]
English:ABRASIVE, POLISHING METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE[2011/29]
French:ABRASIF, PROCÉDÉ DE POLISSAGE ET PROCÉDÉ DE FABRICATION DE DISPOSITIF À CIRCUIT INTÉGRÉ À SEMI-CONDUCTEURS[2011/29]
Entry into regional phase03.05.2011Translation filed 
05.05.2011National basic fee paid 
05.05.2011Search fee paid 
05.05.2011Designation fee(s) paid 
05.05.2011Examination fee paid 
Examination procedure05.05.2011Examination requested  [2011/29]
15.12.2012Application deemed to be withdrawn, date of legal effect  [2013/26]
24.01.2013Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time  [2013/26]
Fees paidRenewal fee
28.10.2011Renewal fee patent year 03
30.10.2012Renewal fee patent year 04
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Documents cited:Search[XYI]EP1860688  (ASAHI GLASS CO LTD [JP], et al) [X] 1,3-6,9-14,17 * paragraphs [0015] - [0020] - [0023] - [0043] - [0046]; figures 1a,1b * [Y] 2 [I] 7,8,15,16;
 [Y]US2006088976  (SIN GARRETT H [US], et al) [Y] 2 * paragraphs [0029] - [0051]; figures 2A-2D *;
 [X]WO2008032681  (ASAHI GLASS CO LTD [JP], et al) [X] 10-16 * paragraphs [0032] , [0034] , [0042] - [0057] * * paragraphs [0077] - [0079]; example 1 * * paragraph [0081]; example 3 * * paragraph [0084]; examples 6,8 * * paragraph [0085]; example 9 *;
 [XI]EP1865546  (ASAHI GLASS CO LTD [JP], et al) [X] 10-14 * paragraphs [0022] , [0034] , [0035] , [0038] - [0048] * [I] 15,16;
 [A]EP1705701  (FUJI PHOTO FILM CO LTD [JP]) [A] 2 * paragraphs [0005] , [0010] - [0014] - [0175] *
International search[X]WO2006103858  (ASAHI GLASS CO LTD [JP], et al);
 [X]WO2007138975  (ASAHI GLASS CO LTD [JP], et al);
 [Y]JPH10163140  (NIPPON STEEL CORP)
by applicantJP3457144B
 JPH1112561
 JP2001035818
 JP2008286366
    - L. BAUD, L. CANAVARI, C. ROMANELLI, G. SPINOLO, M. RIVOIRE, "Planarization of the Poly-Si gate for Non Volatile Memories", INTERNATIONAL CONFERENCE OF PLANARIZATION/CMP TECHNOLOGY PROCEEDINGS, (200710), pages 87 - 91
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.