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Extract from the Register of European Patents

EP About this file: EP2280418

EP2280418 - MOS-gated device having a buried gate and process for forming same [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  30.12.2011
Database last updated on 20.09.2024
Most recent event   Tooltip30.12.2011Application deemed to be withdrawnpublished on 01.02.2012  [2012/05]
Applicant(s)For all designated states
Intersil Corporation
2401 Palm Bay Road, N.N. Palm Bay
Florida 32905 / US
[2011/05]
Inventor(s)01 / Kocon, Christopher
16 Grace Drive
Plains, PA 18705 / US
02 / Zeng, Jun
150 Catalpa Avenue
Mountaintop, PA 18707 / US
 [2011/05]
Representative(s)Lucke, Andreas
Boehmert & Boehmert
Anwaltspartnerschaft mbB
Pettenkoferstrasse 22
80336 München / DE
[N/P]
Former [2011/05]Lucke, Andreas
Forrester & Boehmert Pettenkoferstrasse 20-22
80336 München / DE
Application number, filing date10180114.003.02.2000
[2011/05]
Priority number, dateUS1999026041101.03.1999         Original published format: US 260411
[2011/05]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP2280418
Date:02.02.2011
Language:EN
[2011/05]
Search report(s)(Supplementary) European search report - dispatched on:EP01.12.2010
ClassificationIPC:H01L29/78, H01L29/739, H01L29/74, H01L21/336, H01L21/331, H01L21/332
[2011/05]
CPC:
H01L29/0696 (EP,US); H01L29/4236 (EP,KR,US); H01L29/66348 (EP,US);
H01L29/66734 (EP,KR,US); H01L29/7397 (EP,US); H01L29/7813 (EP,KR,US)
Designated contracting statesDE,   DK,   FR,   GB,   IT [2011/05]
TitleGerman:MOS-Anordnung mit einer vergrabenen Gate und Verfahren zur Herstellung[2011/05]
English:MOS-gated device having a buried gate and process for forming same[2011/05]
French:Dispositif MOS à grille enterrée et procédé pour sa fabrication[2011/05]
Examination procedure02.08.2011Application deemed to be withdrawn, date of legal effect  [2012/05]
08.09.2011Despatch of communication that the application is deemed to be withdrawn, reason: examination fee not paid in time  [2012/05]
Parent application(s)   TooltipEP00102398.5  / EP1033759
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued (EP20000102398) is  04.11.2004
Fees paidRenewal fee
27.09.2010Renewal fee patent year 03
27.09.2010Renewal fee patent year 04
27.09.2010Renewal fee patent year 05
27.09.2010Renewal fee patent year 06
27.09.2010Renewal fee patent year 07
27.09.2010Renewal fee patent year 08
27.09.2010Renewal fee patent year 09
27.09.2010Renewal fee patent year 10
27.09.2010Renewal fee patent year 11
23.02.2011Renewal fee patent year 12
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[IA]JPH02144971  (HITACHI LTD) [I] 1,7 * Abs.Fig. and corresponding text * [A] 2-6,8-13;
 [A]US5828100  (TAMBA AKIHIKO [JP], et al) [A] 1-13 * Fig.2 and corresponding text *
 [T]  - B.Jayant Baliga, Power semiconductor devices, USA, PWS Publishing Company, (19951231), XP002606674 [T] * pgs.410, second and third pars., pg.412, third par., pg.414, second and third par. and pg.417 first complete par. * * Section 7.10.1 * * pg. 410, 2nd. par *
 [T]  - W.Till and J.Luxon, Integrated Circuits: materials, devices and fabrication, USA, Prentice-Hall Inc. N.J. 07632, (19821231), XP002606675 [T] * Fig. 8.3 and corresponding text, pgs. 187-199 *
 [T]  - DELEONIBUS S, "Is there LOCOS after LOCOS?", SOLID STATE ELECTRONICS, ELSEVIER SCIENCE PUBLISHERS, BARKING, GB, (19970701), vol. 41, no. 7, doi:10.1016/S0038-1101(97)00017-8, ISSN 0038-1101, pages 1027 - 1039, XP004075376 [T] * Fig.4 and Section 4 *

DOI:   http://dx.doi.org/10.1016/S0038-1101(97)00017-8
 [IA]  - MATSUMOTO S ET AL, "A HIGH-PERFORMANCE SELF-ALIGNED UMOSFET WITH A VERTICAL TRENCH CONTACT STRUCTURE", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE, NEW YORK, NY, USA, (199405), vol. 41, no. 5, ISSN 0018-9383, pages 814 - 818, XP000483880 [I] 1,7 * Fig.2 and corresponding text;; figure 1B * [A] 2-6,8-13

DOI:   http://dx.doi.org/10.1109/16.285036
 [AD]  - BULUCEA C ET AL, "TRENCH DMOS TRANSISTOR TECHNOLOGY FOR HIGH-CURRENT (100 A RANGE) SWITCHING", SOLID STATE ELECTRONICS, ELSEVIER SCIENCE PUBLISHERS, BARKING, GB, (19910501), vol. 34, no. 5, doi:10.1016/0038-1101(91)90153-P, ISSN 0038-1101, pages 493 - 507, XP000201893 [AD] 1-13 * Figs.3 and 6 *

DOI:   http://dx.doi.org/10.1016/0038-1101(91)90153-P
by applicant   - BULUCEA; ROSSEN, "Trench DMOS Transistor Technology for High-Current (100 A Range) Switching", SOLID-STATE ELECTRONICS, (1991), vol. 34, no. 5, pages 493 - 507
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.