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EP2278506
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EP About this file: EP2278506
| EP2278506 - Method and apparatus for automated circuit design [Right-click to bookmark this link] | Status | The application has been refused Status updated on 07.02.2020 Database last updated on 12.07.2024 | |
| Former | Examination is in progress Status updated on 05.05.2017 | Most recent event Tooltip | 07.02.2020 | Refusal of application | published on 11.03.2020 [2020/11] | Applicant(s) | For all designated states Synopsys, Inc. 700 E. Middlefield Road Mountain View, CA 94043 / US | [2011/04] | Inventor(s) | 01 /
McElvain, Kenneth S. 1160 May Brown Avenue Menlo Park, CA 94025 / US | 02 /
Crews, Andrew 1062 Lily Avenue Sunnyvale, CA 94086 / US | 03 /
Ramachandran, Champaka 10294 Miner Place Cupertino, CA 95014 / US | [2011/04] | Representative(s) | Potter, Julian Mark, et al WP Thompson 138 Fetter Lane London EC4A 1BT / GB | [N/P] |
| Former [2013/14] | Potter, Julian Mark, et al WP Thompson 55 Drury Lane London WC2B 5SQ / GB | ||
| Former [2011/04] | Bartle, Robin Jonathan W.P. Thompson & Co. Coopers Building Church Street Liverpool L1 3AB / GB | Application number, filing date | 10181404.4 | 28.05.2004 | [2011/04] | Priority number, date | US20030475059P | 30.05.2003 Original published format: US 475059 P | US20040856280 | 27.05.2004 Original published format: US 856280 | [2011/04] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP2278506 | Date: | 26.01.2011 | Language: | EN | [2011/04] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 30.11.2010 | Classification | IPC: | G06F17/50 | [2011/04] | CPC: |
G06F30/3312 (EP,US);
G06F30/327 (EP,US);
G06F30/39 (EP,US);
G06F30/392 (EP,US);
G06F30/398 (US);
G06F2119/12 (US)
| Designated contracting states | DE, FR, GB [2011/04] | Title | German: | Verfahren und Vorrichtung zum automatischen Entwurf von Schaltungen | [2011/04] | English: | Method and apparatus for automated circuit design | [2011/04] | French: | Procédé et appareil de conception automatique de circuit | [2011/04] | Examination procedure | 01.07.2011 | Amendment by applicant (claims and/or description) | 01.07.2011 | Examination requested [2011/32] | 08.05.2017 | Despatch of a communication from the examining division (Time limit: M04) | 18.09.2017 | Reply to a communication from the examining division | 23.09.2019 | Application refused, date of legal effect [ N /P ] | 23.09.2019 | Application refused, date of legal effect [2020/11] | 23.09.2019 | Date of oral proceedings | 23.10.2019 | Despatch of communication that the application is refused, reason: substantive examination [ N /P ] | 23.10.2019 | Despatch of communication that the application is refused, reason: substantive examination [2020/11] | 23.10.2019 | Minutes of oral proceedings despatched | Parent application(s) Tooltip | EP04753640.4 / EP1634209 | Divisional application(s) | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued (EP20040753640) is 13.02.2007 | Fees paid | Renewal fee | 28.09.2010 | Renewal fee patent year 03 | 28.09.2010 | Renewal fee patent year 04 | 28.09.2010 | Renewal fee patent year 05 | 28.09.2010 | Renewal fee patent year 06 | 28.09.2010 | Renewal fee patent year 07 | 25.05.2011 | Renewal fee patent year 08 | 25.05.2012 | Renewal fee patent year 09 | 28.05.2013 | Renewal fee patent year 10 | 27.05.2014 | Renewal fee patent year 11 | 27.05.2015 | Renewal fee patent year 12 | 10.05.2016 | Renewal fee patent year 13 | 10.05.2017 | Renewal fee patent year 14 | 11.05.2018 | Renewal fee patent year 15 | 15.05.2019 | Renewal fee patent year 16 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [I]US5666290 (LI YING-MENG [US], et al) [I] 1-16 * the whole document *; | [I]US5978572 (TOYONAGA MASAHIKO [JP], et al) [I] 1-16 * the whole document *; | [I] - COUDERT O, "Timing and design closure in physical design flows", QUALITY ELECTRONIC DESIGN, 2002. PROCEEDINGS. INTERNATIONAL SYMPOSIUM ON 18-21 MARCH 2002, PISCATAWAY, NJ, USA,IEEE, (20020318), ISBN 978-0-7695-1561-8, pages 511 - 516, XP010589410 [I] 1-16 * the whole document * | [I] - CHIEH CHANGFAN ET AL, "Timing optimization on routed designs with incremental placement and routing characterization", IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS IEEE USA, (200002), vol. 19, no. 2, ISSN 0278-0070, pages 188 - 196, XP002304008 [I] 1-16 * the whole document * DOI: http://dx.doi.org/10.1109/43.828547 |