EP2416361 - Arrays for CMOS imagers and their method of manufacturing [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 09.11.2018 Database last updated on 11.09.2024 | |
Former | The patent has been granted Status updated on 01.12.2017 | ||
Former | Grant of patent is intended Status updated on 09.07.2017 | Most recent event Tooltip | 26.06.2020 | Lapse of the patent in a contracting state New state(s): MK | published on 29.07.2020 [2020/31] | Applicant(s) | For all designated states IMEC VZW Kapeldreef 75 3001 Leuven / BE | [2017/52] |
Former [2012/06] | For all designated states IMEC Kapeldreef 75 3001 Leuven / BE | Inventor(s) | 01 /
De Munck, Koen IMEC Hertogstraat 147 B503 B-3001 Leuven / BE | 02 /
Minoglou, Kiki IMEC Parkstraat 133/5 B-3000 Leuven / BE | 03 /
De Vos, Joeri IMEC Donkerstraat 32 B-3400 Neerwinden / BE | [2012/06] | Representative(s) | AWA Sweden AB Box 1066 251 10 Helsingborg / SE | [N/P] |
Former [2018/01] | Awapatent AB P.O. Box 1066 251 10 Helsingborg / SE | ||
Former [2012/06] | Bird Goën & Co Klein Dalenstraat 42A 3020 Winksele / BE | Application number, filing date | 11176322.3 | 02.08.2011 | [2012/06] | Priority number, date | US20100369846P | 02.08.2010 Original published format: US 369846 P | [2012/06] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP2416361 | Date: | 08.02.2012 | Language: | EN | [2012/06] | Type: | A3 Search report | No.: | EP2416361 | Date: | 13.11.2013 | Language: | EN | [2013/46] | Type: | B1 Patent specification | No.: | EP2416361 | Date: | 03.01.2018 | Language: | EN | [2018/01] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 16.10.2013 | Classification | IPC: | H01L27/146 | [2012/06] | CPC: |
H01L27/14683 (EP,US);
H01L27/1463 (EP,US)
| Designated contracting states | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR [2018/01] |
Former [2012/06] | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR | Title | German: | Arrays für CMOS-Bildgeräte und ihr Herstellungsverfahren | [2012/06] | English: | Arrays for CMOS imagers and their method of manufacturing | [2012/06] | French: | Réseaux pour imageurs CMOS et son procédé de fabrication | [2012/06] | Examination procedure | 13.05.2014 | Amendment by applicant (claims and/or description) | 13.05.2014 | Examination requested [2014/26] | 10.07.2017 | Communication of intention to grant the patent | 09.11.2017 | Fee for grant paid | 09.11.2017 | Fee for publishing/printing paid | 09.11.2017 | Receipt of the translation of the claim(s) | Divisional application(s) | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 10.07.2017 | Opposition(s) | 05.10.2018 | No opposition filed within time limit [2018/50] | Fees paid | Renewal fee | 22.08.2013 | Renewal fee patent year 03 | 26.08.2014 | Renewal fee patent year 04 | 25.08.2015 | Renewal fee patent year 05 | 24.08.2016 | Renewal fee patent year 06 | 23.08.2017 | Renewal fee patent year 07 |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | HU | 02.08.2011 | AL | 03.01.2018 | AT | 03.01.2018 | CY | 03.01.2018 | CZ | 03.01.2018 | DK | 03.01.2018 | EE | 03.01.2018 | ES | 03.01.2018 | FI | 03.01.2018 | HR | 03.01.2018 | IT | 03.01.2018 | LT | 03.01.2018 | LV | 03.01.2018 | MC | 03.01.2018 | MK | 03.01.2018 | NL | 03.01.2018 | PL | 03.01.2018 | PT | 03.01.2018 | RO | 03.01.2018 | RS | 03.01.2018 | SE | 03.01.2018 | SI | 03.01.2018 | SK | 03.01.2018 | SM | 03.01.2018 | TR | 03.01.2018 | BG | 03.04.2018 | NO | 03.04.2018 | GR | 04.04.2018 | IS | 03.05.2018 | IE | 02.08.2018 | LU | 02.08.2018 | MT | 02.08.2018 | BE | 31.08.2018 | CH | 31.08.2018 | LI | 31.08.2018 | [2020/31] |
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NO | 03.04.2018 | Documents cited: | Search | [XYI]US2005184353 (MOULI CHANDRA [US]) [X] 10-12,14,15 * paragraphs [0010] , [0027] , [0 28] , [0 30] , [0 31] , [0 39] - [0042] * * figure 4 * [Y] 5,6,13 [I] 1-4,7-9; | [I]US2006043525 (MOULI CHANDRA [US]) [I] 10-12,15 * paragraphs [0051] - [0055] - [0057] * * figures 7-11 *; | [X]EP1750308 (AVAGO TECHNOLOGIES SENSOR IP S [SG]) [X] 10-12 * paragraphs [0017] - [0023] * * figures 3,4 *; | [XP]EP2320463 (ST MICROELECTRONICS SA [FR], et al) [XP] 10-13 * paragraphs [0023] , [0025] - [0039] ** figures 2-9 *; | [XY] - KYRIAKI MINOGLOU ET AL, "Reduction of Electrical Crosstalk in Hybrid Backside Illuminated CMOS Imagers using Deep Trench Isolation", INTERCONNECT TECHNOLOGY CONFERENCE, 2008. IITC 2008. INTERNATIONAL, IEEE, PISCATAWAY, NJ, USA, (20080601), ISBN 978-1-4244-1911-1, pages 129 - 131, XP031274517 [X] 10-15 * Chapter "Device fabrication" * * figures 2b, 3 * [Y] 5,6,13 | [X] - KOEN DE MUNCK ET AL, "High performance Hybrid and Monolithic Backside Thinned CMOS Imagers realized using a new integration process", ELECTRON DEVICES MEETING, 2006. IEDM '06. INTERNATIONAL, IEEE, PI, (20061201), ISBN 978-1-4244-0438-4, pages 1 - 4, XP031078408 [X] 10-15 * Chapter "Introduction concept" * * figure 3 * | by applicant | - K. DE MUNCK ET AL., "High performance hybrid and monolithic backside thinned CMOS imagers realized using a new integration process", IEEE INTERNATIONAL ELECTRON DEVICES MEETING, (200612), pages 139 - 142 | - K. MINOGLOU ET AL., "Reduction of electrical crosstalk in hybrid backside illuminated CMOS imagers using deep trench isolation", IITC CONF., (200806), pages 139 - 142 |