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Extract from the Register of European Patents

EP About this file: EP2549283

EP2549283 - SEMICONDUCTOR DEVICE, DETECTION METHOD, AND STORAGE MEDIUM [Right-click to bookmark this link]
Former [2013/04]SEMICONDUCTOR DEVICE, DETECTION METHOD, AND PROGRAM
[2021/12]
StatusThe application is deemed to be withdrawn
Status updated on  26.11.2021
Database last updated on 25.09.2024
FormerGrant of patent is intended
Status updated on  09.03.2021
FormerExamination is in progress
Status updated on  29.06.2020
Most recent event   Tooltip26.11.2021Application deemed to be withdrawnpublished on 29.12.2021  [2021/52]
Applicant(s)For all designated states
Kyushu Institute of Technology
1-1, Sensui-cho Tobata-ku
Kitakyushu-shi, Fukuoka 804-8550 / JP
For all designated states
National University Corporation Nara Institute of Science and Technology
8916-5, Takayamacho
Ikoma-shi, Nara 630-0192 / JP
For all designated states
Tokyo Metropolitan University
2-8-1, Nishi-Shinjuku
Shinjuku-ku
Tokyo 163-8001 / JP
[N/P]
Former [2013/04]For all designated states
Kyushu Institute of Technology
1-1, Sensui-cho Tobata-ku
Kitakyushu-shi, Fukuoka 804-8550 / JP
For all designated states
National University Corporation Nara Institute of Science and Technology
8916-5, Takayamacho
Ikoma-shi, Nara 630-0192 / JP
For all designated states
Tokyo Metropolitan University
2-8-1, Nishi-Shinjuku Shinjuku-ku
Tokyo 163-8001 / JP
Inventor(s)01 / SATO, Yasuo
c/o Kyushu Institute of Technology
680-4, Kawazu
Iizuka-shi
Fukuoka 820-8502 / JP
02 / KAJIHARA, Seiji
c/o Kyushu Institute of Technology
680-4, Kawazu
Iizuka-shi
Fukuoka 820-8502 / JP
03 / INOUE, Michiko
c/o National University Corporation Nara Institute
of Science and Technology
8916-5, Takayama-cho
Ikoma-shi
Nara 630-0192 / JP
04 / YONEDA, Tomokazu
c/o National University Corporation Nara Institute
of Science and Technology
8916-5, Takayama-cho
Ikoma-shi
Nara 630-0192 / JP
05 / YI, Hyunbean
c/o National University Corporation Nara Institute
of Science and Technology
8916-5, Takayama-cho
Ikoma-shi
Nara 630-0192 / JP
06 / MIURA, Yukiya
c/o Tokyo Metropolitan University
6-6, Asahigaoka
Hino-shi
Tokyo 191-0065 / JP
 [2013/04]
Representative(s)Plougmann Vingtoft a/s
Strandvejen 70
2900 Hellerup / DK
[N/P]
Former [2013/04]Plougmann & Vingtoft A/S
Rued Langgaards Vej 8
2300 Copenhagen S / DK
Application number, filing date11756223.114.03.2011
WO2011JP55900
Priority number, dateJP2010005731015.03.2010         Original published format: JP 2010057310
[2013/04]
Filing languageJA
Procedural languageEN
PublicationType: A1 Application with search report
No.:WO2011115038
Date:22.09.2011
Language:JA
[2011/38]
Type: A1 Application with search report 
No.:EP2549283
Date:23.01.2013
Language:EN
[2013/04]
Search report(s)International search report - published on:JP22.09.2011
(Supplementary) European search report - dispatched on:EP23.05.2017
ClassificationIPC:G01R31/28, G01R31/30
[2017/25]
CPC:
G01R31/2884 (EP,KR,US); G01R19/2503 (KR); G01R19/252 (KR);
G01R31/2856 (EP,US); G01R31/2874 (KR); G01R31/2879 (KR);
G01R31/2882 (KR); G01R31/3016 (EP,KR,US) (-)
Former IPC [2013/04]G01R31/28, H01L21/822, H01L27/04
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2013/04]
TitleGerman:HALBLEITERBAUELEMENT, ERKENNUNGSVERFAHREN UND SPEICHERMEDIUM[2021/12]
English:SEMICONDUCTOR DEVICE, DETECTION METHOD, AND STORAGE MEDIUM[2021/12]
French:DISPOSITIF À SEMI-CONDUCTEUR, PROCÉDÉ DE DÉTECTION ET SUPPORT DE STOCKAGE[2021/12]
Former [2013/04]HALBLEITERBAUELEMENT SOWIE ERKENNUNGSVERFAHREN UND PROGRAMM DAFÜR
Former [2013/04]SEMICONDUCTOR DEVICE, DETECTION METHOD, AND PROGRAM
Former [2013/04]DISPOSITIF À SEMI-CONDUCTEUR, PROCÉDÉ DE DÉTECTION ET PROGRAMME
Entry into regional phase11.10.2012Translation filed 
11.10.2012National basic fee paid 
11.10.2012Search fee paid 
11.10.2012Designation fee(s) paid 
11.10.2012Examination fee paid 
Examination procedure11.10.2012Examination requested  [2013/04]
22.12.2017Amendment by applicant (claims and/or description)
02.07.2020Despatch of a communication from the examining division (Time limit: M06)
15.12.2020Reply to a communication from the examining division
10.03.2021Communication of intention to grant the patent
21.07.2021Application deemed to be withdrawn, date of legal effect  [2021/52]
10.08.2021Despatch of communication that the application is deemed to be withdrawn, reason: fee for grant / fee for printing not paid in time  [2021/52]
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is  02.07.2020
Fees paidRenewal fee
26.03.2013Renewal fee patent year 03
21.03.2014Renewal fee patent year 04
24.03.2015Renewal fee patent year 05
25.03.2016Renewal fee patent year 06
24.03.2017Renewal fee patent year 07
23.03.2018Renewal fee patent year 08
20.02.2019Renewal fee patent year 09
24.03.2020Renewal fee patent year 10
20.01.2021Renewal fee patent year 11
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Documents cited:Search[I]US2009108863  (GONZALEZ CHRISTOPHER [US], et al) [I] 1-13 * figures 1,2 * * paragraph [0026] - paragraph [0027] * * paragraph [0031] - paragraph [0037] * * paragraph [0044] *;
 [A]US5795068  (CONN JR ROBERT O [US]) [A] 1-13 * abstract *;
 [A]US2006223201  (LIU JONATHAN H [US], et al) [A] 1-13 * abstract * * paragraph [0066] *
International search[A]JPH09292436  (MATSUSHITA ELECTRIC IND CO LTD);
 [A]JPH07191095  (TEKTRONIX INC);
 [A]JPH0961503  (ADVANTEST CORP);
 [A]JP2003068865  (SONY CORP)
by applicantJP2003068865
 JP2010524101
    - SATO ET AL., "A Survey of Approaches for High Field Reliability", REAJ, vol. 31, no. 7, pages 514 - 519
    - Y. SATO ET AL., "A Circuit Failure Prediction Mechanism (DART) for High Field Reliability", THE 8TH IEEE INTERNATIONAL CONFERENCE ON ASIC, (2009), pages 581 - 584, XP031578952
    - T. VO ET AL., "Design for Board and System Level Structure Test and Diagnosis", PROC. INTL. TEST CONF., (2006), pages 1 - 10
    - Y. LI ET AL., "CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns", PROC. DESIGN AUTOMATION AND TEST IN EUROPE, (2008), pages 885 - 890, XP031241898
    - O. KHAN ET AL., "A Self-Adaptive System Architecture to Address transistor Aging", PROC. DESIGN AUTOMATION AND TEST IN EUROPE, (2009), doi:doi:10.1109/DATE.2009.5090637, pages 81 - 86, XP032317470

DOI:   http://dx.doi.org/10.1109/DATE.2009.5090637
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.