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Extract from the Register of European Patents

EP About this file: EP2719081

EP2719081 - MODIFIED DYNAMIC ELEMENT MATCHING FOR REDUCED LATENCY IN A PIPELINE ANALOG TO DIGITAL CONVERTER [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  15.06.2018
Database last updated on 19.10.2024
FormerThe patent has been granted
Status updated on  07.07.2017
FormerGrant of patent is intended
Status updated on  24.01.2017
Most recent event   Tooltip17.07.2020Lapse of the patent in a contracting state
New state(s): AL		published on 19.08.2020  [2020/34]
Applicant(s)For all designated states
Microchip Technology Incorporated
2355 West Chandler Boulevard
Chandler, AZ 85224-6199 / US
[2014/16]
Inventor(s)01 / MEACHAM, Daniel
2131 David Way
Del Mar, CA 92014 / US
02 / PANIGADA, Andrea
6625 Radcliffe Drive
San Diego, CA 92122 / US
03 / GRILO, Jorge
7045 Marsh Wren Street
San Diego, CA 92122 / US
 [2014/16]
Representative(s)sgb europe
Bergstrasse 31
82069 Hohenschäftlarn / DE
[N/P]
Former [2017/32]Grubert, Andreas, et al
c/o Westphal, Mussgnug & Partner
Patentanwälte mbB
Herzog-Wilhelm-Straße 26
80331 München / DE
Former [2014/16]Grubert, Andreas
King & Spalding 125 Old Broad Street
London EC2N 1AR / GB
Application number, filing date12731225.407.06.2012
[2017/32]
WO2012US41269
Priority number, dateUS201161495369P09.06.2011         Original published format: US 201161495369 P
US20121348986506.06.2012         Original published format: US201213489865
[2014/16]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report
No.:WO2012170642
Date:13.12.2012
Language:EN
[2012/50]
Type: A1 Application with search report 
No.:EP2719081
Date:16.04.2014
Language:EN
The application published by WIPO in one of the EPO official languages on 13.12.2012 takes the place of the publication of the European patent application.
[2014/16]
Type: B1 Patent specification 
No.:EP2719081
Date:09.08.2017
Language:EN
[2017/32]
Search report(s)International search report - published on:EP13.12.2012
ClassificationIPC:H03M1/06, H03M1/16
[2017/05]
CPC:
H03M1/0673 (EP,US); H03M1/06 (KR); H03M1/0641 (EP,US);
H03M1/164 (EP,US)
Former IPC [2014/16]H03M1/06
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2014/16]
Extension statesBANot yet paid
MENot yet paid
TitleGerman:MODIFIZIERTE DYNAMISCHE ELEMENTANPASSUNG ZUR VERRINGERUNG DER LATENZ BEI EINEM ANALOG-DIGITAL-WANDLER EINER PIPELINE[2014/16]
English:MODIFIED DYNAMIC ELEMENT MATCHING FOR REDUCED LATENCY IN A PIPELINE ANALOG TO DIGITAL CONVERTER[2014/16]
French:MISE EN CORRESPONDANCE D'UN ÉLÉMENT DYNAMIQUE MODIFIÉ AFIN DE RÉDUIRE LE TEMPS D'ATTENTE DANS UN CONVERTISSEUR ANALOGIQUE-NUMÉRIQUE EN PIPELINE[2014/16]
Entry into regional phase08.01.2014National basic fee paid 
08.01.2014Designation fee(s) paid 
08.01.2014Examination fee paid 
Examination procedure08.01.2014Amendment by applicant (claims and/or description)
08.01.2014Examination requested  [2014/16]
25.01.2017Communication of intention to grant the patent
26.05.2017Fee for grant paid
26.05.2017Fee for publishing/printing paid
26.05.2017Receipt of the translation of the claim(s)
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is  25.01.2017
Opposition(s)11.05.2018No opposition filed within time limit [2018/29]
Fees paidRenewal fee
27.08.2014Renewal fee patent year 03
29.06.2015Renewal fee patent year 04
27.06.2016Renewal fee patent year 05
27.06.2017Renewal fee patent year 06
Penalty fee
Additional fee for renewal fee
30.06.201403   M06   Fee paid on   27.08.2014
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipHU07.06.2012
AL09.08.2017
AT09.08.2017
CY09.08.2017
CZ09.08.2017
DK09.08.2017
EE09.08.2017
ES09.08.2017
FI09.08.2017
HR09.08.2017
IT09.08.2017
LT09.08.2017
LV09.08.2017
MC09.08.2017
MK09.08.2017
NL09.08.2017
PL09.08.2017
PT09.08.2017
RO09.08.2017
RS09.08.2017
SE09.08.2017
SI09.08.2017
SK09.08.2017
SM09.08.2017
TR09.08.2017
BG09.11.2017
NO09.11.2017
GR10.11.2017
IS09.12.2017
[2020/34]
Former [2020/31]HU07.06.2012
AT09.08.2017
CY09.08.2017
CZ09.08.2017
DK09.08.2017
EE09.08.2017
ES09.08.2017
FI09.08.2017
HR09.08.2017
IT09.08.2017
LT09.08.2017
LV09.08.2017
MC09.08.2017
MK09.08.2017
NL09.08.2017
PL09.08.2017
PT09.08.2017
RO09.08.2017
RS09.08.2017
SE09.08.2017
SI09.08.2017
SK09.08.2017
SM09.08.2017
TR09.08.2017
BG09.11.2017
NO09.11.2017
GR10.11.2017
IS09.12.2017
Former [2020/27]HU07.06.2012
AT09.08.2017
CZ09.08.2017
DK09.08.2017
EE09.08.2017
ES09.08.2017
FI09.08.2017
HR09.08.2017
IT09.08.2017
LT09.08.2017
LV09.08.2017
MC09.08.2017
NL09.08.2017
PL09.08.2017
PT09.08.2017
RO09.08.2017
RS09.08.2017
SE09.08.2017
SI09.08.2017
SK09.08.2017
SM09.08.2017
TR09.08.2017
BG09.11.2017
NO09.11.2017
GR10.11.2017
IS09.12.2017
Former [2020/15]AT09.08.2017
CZ09.08.2017
DK09.08.2017
EE09.08.2017
ES09.08.2017
FI09.08.2017
HR09.08.2017
IT09.08.2017
LT09.08.2017
LV09.08.2017
MC09.08.2017
NL09.08.2017
PL09.08.2017
RO09.08.2017
RS09.08.2017
SE09.08.2017
SI09.08.2017
SK09.08.2017
SM09.08.2017
TR09.08.2017
BG09.11.2017
NO09.11.2017
GR10.11.2017
IS09.12.2017
Former [2019/15]AT09.08.2017
CZ09.08.2017
DK09.08.2017
EE09.08.2017
ES09.08.2017
FI09.08.2017
HR09.08.2017
IT09.08.2017
LT09.08.2017
LV09.08.2017
MC09.08.2017
NL09.08.2017
PL09.08.2017
RO09.08.2017
RS09.08.2017
SE09.08.2017
SI09.08.2017
SK09.08.2017
SM09.08.2017
BG09.11.2017
NO09.11.2017
GR10.11.2017
IS09.12.2017
Former [2018/39]AT09.08.2017
CZ09.08.2017
DK09.08.2017
EE09.08.2017
ES09.08.2017
FI09.08.2017
HR09.08.2017
IT09.08.2017
LT09.08.2017
LV09.08.2017
NL09.08.2017
PL09.08.2017
RO09.08.2017
RS09.08.2017
SE09.08.2017
SI09.08.2017
SK09.08.2017
SM09.08.2017
BG09.11.2017
NO09.11.2017
GR10.11.2017
IS09.12.2017
Former [2018/24]AT09.08.2017
CZ09.08.2017
DK09.08.2017
EE09.08.2017
ES09.08.2017
FI09.08.2017
HR09.08.2017
IT09.08.2017
LT09.08.2017
LV09.08.2017
NL09.08.2017
PL09.08.2017
RO09.08.2017
RS09.08.2017
SE09.08.2017
SK09.08.2017
SM09.08.2017
BG09.11.2017
NO09.11.2017
GR10.11.2017
IS09.12.2017
Former [2018/23]AT09.08.2017
CZ09.08.2017
DK09.08.2017
EE09.08.2017
ES09.08.2017
FI09.08.2017
HR09.08.2017
LT09.08.2017
LV09.08.2017
NL09.08.2017
PL09.08.2017
RO09.08.2017
RS09.08.2017
SE09.08.2017
SK09.08.2017
BG09.11.2017
NO09.11.2017
GR10.11.2017
IS09.12.2017
Former [2018/21]AT09.08.2017
CZ09.08.2017
DK09.08.2017
ES09.08.2017
FI09.08.2017
HR09.08.2017
LT09.08.2017
LV09.08.2017
NL09.08.2017
PL09.08.2017
RS09.08.2017
SE09.08.2017
BG09.11.2017
NO09.11.2017
GR10.11.2017
IS09.12.2017
Former [2018/12]AT09.08.2017
ES09.08.2017
FI09.08.2017
HR09.08.2017
LT09.08.2017
LV09.08.2017
NL09.08.2017
PL09.08.2017
RS09.08.2017
SE09.08.2017
BG09.11.2017
NO09.11.2017
GR10.11.2017
IS09.12.2017
Former [2018/11]AT09.08.2017
ES09.08.2017
FI09.08.2017
HR09.08.2017
LT09.08.2017
NL09.08.2017
PL09.08.2017
RS09.08.2017
SE09.08.2017
BG09.11.2017
NO09.11.2017
GR10.11.2017
IS09.12.2017
Former [2018/10]AT09.08.2017
FI09.08.2017
HR09.08.2017
LT09.08.2017
NL09.08.2017
RS09.08.2017
SE09.08.2017
NO09.11.2017
Former [2018/09]FI09.08.2017
LT09.08.2017
NL09.08.2017
SE09.08.2017
NO09.11.2017
Former [2018/08]FI09.08.2017
LT09.08.2017
NL09.08.2017
NO09.11.2017
Former [2018/07]LT09.08.2017
NO09.11.2017
Cited inInternational search[AD]US6734818  (GALTON IAN [US]) [AD] 1-11 * the whole document *;
 [AD]US7602323  (GALTON IAN [US], et al) [AD] 1-11* the whole document *;
 [Y]US2010225513  (LIN CHIA-LIANG [US]) [Y] 1-11 * paragraph [0009] * * paragraph [0020] * * figure 1 *;
 [Y]  - PANIGADA A ET AL, "A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, (20091201), vol. 44, no. 12, doi:10.1109/JSSC.2009.2032637, ISSN 0018-9200, pages 3314 - 3328, XP011285550 [Y] 1-11 * abstract * * page 3317, column L * * figures 11,12 *

DOI:   http://dx.doi.org/10.1109/JSSC.2009.2032637
 [Y]  - JIPENG LI ET AL, "Background calibration techniques for multistage pipelined ADCs with digital redundancy", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: ANALOG AND DIGITALSIGNAL PROCESSING, INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS INC, 345 EAST 47 STREET, NEW YORK, N.Y. 10017, USA, (20030901), vol. 50, no. 9, doi:10.1109/TCSII.2003.816921, ISSN 1057-7130, pages 531 - 538, XP011100966 [Y] 2,4,7,9,11 * page 535 * * page 538, column L * * figure 7 *

DOI:   http://dx.doi.org/10.1109/TCSII.2003.816921
by applicantUS6734818
 US7602323
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