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Extract from the Register of European Patents

EP About this file: EP2620946

EP2620946 - Adaptive programming and erasure methods for analog memory cells [Right-click to bookmark this link]
StatusThe application has been refused
Status updated on  28.09.2018
Database last updated on 24.08.2024
Most recent event   Tooltip28.09.2018Refusal of applicationpublished on 31.10.2018  [2018/44]
Applicant(s)For all designated states
Apple Inc.
One Apple Park Way
Cupertino CA 95014 / US
[2018/31]
Former [2013/31]For all designated states
APPLE INC.
1 Infinite Loop
Cupertino, CA 95014 / US
Inventor(s)01 / Gurgi, Eyal
c/o Apple Inc.
1 Infinite Loop
Cupertino, CA, 95014 / US
02 / Kasorla, Yoav
c/o Apple Inc.
1 Infinite Loop
Cupertino, CA, 95014 / US
03 / Shalvi, Ofir
c/o Apple Inc.
1 Infinite Loop
Cupertino, CA, 95014 / US
 [2013/31]
Representative(s)Lang, Johannes
Bardehle Pagenberg Partnerschaft mbB
Patentanwälte, Rechtsanwälte
Prinzregentenplatz 7
81675 München / DE
[N/P]
Former [2013/31]Lang, Johannes
Bardehle Pagenberg Partnerschaft
Patentanwälte, Rechtsanwälte
Prinzregentenplatz 7
81675 München / DE
Application number, filing date13152130.422.01.2013
[2013/31]
Priority number, dateUS20121335669424.01.2012         Original published format: US201213356694
US20121347148315.05.2012         Original published format: US201213471483
[2013/31]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP2620946
Date:31.07.2013
Language:EN
[2013/31]
Type: A3 Search report 
No.:EP2620946
Date:23.10.2013
Language:EN
[2013/43]
Search report(s)(Supplementary) European search report - dispatched on:EP24.09.2013
ClassificationIPC:G11C29/02, G11C11/56, G11C16/34
[2013/31]
CPC:
G11C11/5628 (EP); G11C11/5635 (EP); G11C16/10 (KR);
G11C16/14 (EP); G11C16/34 (KR); G11C16/3445 (EP);
G11C16/3459 (EP); G11C29/021 (EP); G11C29/028 (EP);
G11C7/10 (KR); G11C2029/0409 (EP) (-)
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2013/31]
Extension statesBANot yet paid
MENot yet paid
TitleGerman:Adaptive Programmier- und Löschverfahren für analoge Speicherzellen[2013/31]
English:Adaptive programming and erasure methods for analog memory cells[2013/31]
French:Procédés de programmation et d'effacement adaptivs pour cellules de mémoire analogiques[2013/31]
Examination procedure22.01.2013Examination requested  [2013/31]
23.04.2014Amendment by applicant (claims and/or description)
10.02.2016Despatch of a communication from the examining division (Time limit: M04)
14.06.2016Reply to a communication from the examining division
30.05.2018Application refused, date of legal effect [2018/44]
30.05.2018Cancellation of oral proceeding that was planned for 31.05.2018
31.05.2018Date of oral proceedings
31.05.2018Date of oral proceedings (cancelled)
12.06.2018Despatch of communication that the application is refused, reason: substantive examination [2018/44]
12.06.2018Minutes of oral proceedings despatched
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is  10.02.2016
Fees paidRenewal fee
13.01.2015Renewal fee patent year 03
11.01.2016Renewal fee patent year 04
11.01.2017Renewal fee patent year 05
15.01.2018Renewal fee patent year 06
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[XA]US7656710  (WONG SAU CHING [US]) [X] 1,2,9,10 * column 6, line 59 - column 16, line 6; figures 2-4E * [A] 3,11;
 [XA]US2006158940  (SHAPPIR ASSAF [IL], et al) [X] 1,3,9,11 * paragraph [0010] * [A] 2,10
by applicant   - BEZ ET AL., "Introduction to Flash Memory", PROCEEDINGS OF THE IEEE, (200304), vol. 91, no. 4, doi:doi:10.1109/JPROC.2003.811702, pages 489 - 502, XP011065131

DOI:   http://dx.doi.org/10.1109/JPROC.2003.811702
    - EITAN ET AL., "Multilevel Flash Cells and their Trade-Offs", PROCEEDINGS OF THE 1996 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM, pages 169 - 172
    - EITAN ET AL., "Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?", PROCEEDINGS OF THE 1999 INTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS (SSDM, (19990921), pages 522 - 524, XP000935199
    - MAAYAN ET AL., "A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate", PROCEEDINGS OF THE 2002 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC 2002, (20020203), pages 100 - 101
    - KIM; KOH; NIS, SERBIA; MONTENEGRO, "Future Memory Technology including Emerging New Memories", PROCEEDINGS OF THE 24TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL, (20040516), vol. 1, doi:doi:10.1109/ICMEL.2004.1314646, pages 377 - 384, XP010709368

DOI:   http://dx.doi.org/10.1109/ICMEL.2004.1314646
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.