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Extract from the Register of European Patents

EP About this file: EP2839378

EP2839378 - SYSTEM AND METHOD FOR MANAGING CACHE COHERENCE IN A NETWORK OF PROCESSORS PROVIDED WITH CACHE MEMORIES [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  10.08.2018
Database last updated on 05.10.2024
FormerThe patent has been granted
Status updated on  01.09.2017
FormerGrant of patent is intended
Status updated on  15.06.2017
FormerRequest for examination was made
Status updated on  05.05.2017
FormerGrant of patent is intended
Status updated on  22.03.2017
Most recent event   Tooltip17.07.2020Lapse of the patent in a contracting state
New state(s): AL		published on 19.08.2020  [2020/34]
Applicant(s)For all designated states
Commissariat à l'Énergie Atomique et aux Énergies Alternatives
25, Rue Leblanc
Bâtiment "Le Ponant D"
75015 Paris / FR
For all designated states
Bull S.A.S.
Rue Jean Jaurès
BP 68
78340 Les Clayes-sous-Bois / FR
[2017/40]
Former [2015/09]For all designated states
Commissariat à l'Énergie Atomique et aux Énergies Alternatives
25, rue Leblanc
Bâtiment "Le Ponant D"
75015 Paris / FR
For all designated states
Bull S.A.S.
Rue Jean Jaurès B.P. 68
78340 Les Clayes sous Bois / FR
Inventor(s)01 / BERNARD, Christian
120 chemin de l'Arny
F-38960 Saint Etienne de Crossey / FR
02 / GUTHMULLER, Eric
29 Vie Etroite
F-38300 Ruy / FR
03 / NGUYEN, Huy Nam
33 Avenue de la Liberté
F-94260 Fresnes / FR
 [2015/09]
Representative(s)Bonnet, Michel
Cabinet Bonnet
93, rue Réaumur - Boîte 10
75002 Paris / FR
[2017/40]
Former [2015/09]Bonnet, Michel
Cabinet Bonnet 93, Rue Réaumur - Boîte 10
75002 Paris / FR
Application number, filing date13720479.812.04.2013
[2017/40]
WO2013FR50802
Priority number, dateFR2012005349816.04.2012         Original published format: FR 1253498
[2015/09]
Filing languageFR
Procedural languageFR
PublicationType: A1 Application with search report
No.:WO2013156716
Date:24.10.2013
Language:FR
[2013/43]
Type: A1 Application with search report 
No.:EP2839378
Date:25.02.2015
Language:FR
The application published by WIPO in one of the EPO official languages on 24.10.2013 takes the place of the publication of the European patent application.
[2015/09]
Type: B1 Patent specification 
No.:EP2839378
Date:04.10.2017
Language:FR
[2017/40]
Search report(s)International search report - published on:EP24.10.2013
ClassificationIPC:G06F12/0813, G06F12/0817
[2017/09]
CPC:
G06F12/0817 (EP,US); G06F12/0828 (US); G06F12/0813 (US);
G06F2212/254 (EP,US); G06F2212/621 (US)
Former IPC [2015/09]G06F12/08
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2015/09]
Extension statesBANot yet paid
MENot yet paid
TitleGerman:SYSTEM UND VERFAHREN ZUR VERWALTUNG VON CACHE-KOHÄRENZ IN EINEM NETZWERK AUS MIT CACHE-SPEICHERN AUSGERÜSTETEN PROZESSOREN[2015/09]
English:SYSTEM AND METHOD FOR MANAGING CACHE COHERENCE IN A NETWORK OF PROCESSORS PROVIDED WITH CACHE MEMORIES[2015/09]
French:SYSTEME ET PROCEDE DE GESTION D'UNE COHERENCE DE CACHES DANS UN RESEAU DE PROCESSEURS MUNIS DE MEMOIRES CACHES[2015/09]
Entry into regional phase13.10.2014National basic fee paid 
13.10.2014Designation fee(s) paid 
13.10.2014Examination fee paid 
Examination procedure13.10.2014Examination requested  [2015/09]
23.03.2017Communication of intention to grant the patent
25.04.2017Disapproval of the communication of intention to grant the patent by the applicant or resumption of examination proceedings by the EPO
12.06.2017Communication of intention to grant the patent
24.08.2017Fee for grant paid
24.08.2017Fee for publishing/printing paid
24.08.2017Receipt of the translation of the claim(s)
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is  23.03.2017
Opposition(s)05.07.2018No opposition filed within time limit [2018/37]
Fees paidRenewal fee
16.04.2015Renewal fee patent year 03
15.04.2016Renewal fee patent year 04
20.04.2017Renewal fee patent year 05
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipHU12.04.2013
AL04.10.2017
AT04.10.2017
CY04.10.2017
CZ04.10.2017
DK04.10.2017
EE04.10.2017
ES04.10.2017
FI04.10.2017
HR04.10.2017
IT04.10.2017
LT04.10.2017
LV04.10.2017
MC04.10.2017
MK04.10.2017
MT04.10.2017
NL04.10.2017
PL04.10.2017
PT04.10.2017
RO04.10.2017
RS04.10.2017
SE04.10.2017
SI04.10.2017
SK04.10.2017
SM04.10.2017
TR04.10.2017
BG04.01.2018
NO04.01.2018
GR05.01.2018
IS04.02.2018
IE12.04.2018
LU12.04.2018
BE30.04.2018
CH30.04.2018
LI30.04.2018
[2020/34]
Former [2020/31]HU12.04.2013
AT04.10.2017
CY04.10.2017
CZ04.10.2017
DK04.10.2017
EE04.10.2017
ES04.10.2017
FI04.10.2017
HR04.10.2017
IT04.10.2017
LT04.10.2017
LV04.10.2017
MC04.10.2017
MK04.10.2017
MT04.10.2017
NL04.10.2017
PL04.10.2017
PT04.10.2017
RO04.10.2017
RS04.10.2017
SE04.10.2017
SI04.10.2017
SK04.10.2017
SM04.10.2017
TR04.10.2017
BG04.01.2018
NO04.01.2018
GR05.01.2018
IS04.02.2018
IE12.04.2018
LU12.04.2018
BE30.04.2018
CH30.04.2018
LI30.04.2018
Former [2020/28]HU12.04.2013
AT04.10.2017
CZ04.10.2017
DK04.10.2017
EE04.10.2017
ES04.10.2017
FI04.10.2017
HR04.10.2017
IT04.10.2017
LT04.10.2017
LV04.10.2017
MC04.10.2017
MT04.10.2017
NL04.10.2017
PL04.10.2017
PT04.10.2017
RO04.10.2017
RS04.10.2017
SE04.10.2017
SI04.10.2017
SK04.10.2017
SM04.10.2017
TR04.10.2017
BG04.01.2018
NO04.01.2018
GR05.01.2018
IS04.02.2018
IE12.04.2018
LU12.04.2018
BE30.04.2018
CH30.04.2018
LI30.04.2018
Former [2020/16]AT04.10.2017
CZ04.10.2017
DK04.10.2017
EE04.10.2017
ES04.10.2017
FI04.10.2017
HR04.10.2017
IT04.10.2017
LT04.10.2017
LV04.10.2017
MC04.10.2017
MT04.10.2017
NL04.10.2017
PL04.10.2017
RO04.10.2017
RS04.10.2017
SE04.10.2017
SI04.10.2017
SK04.10.2017
SM04.10.2017
TR04.10.2017
BG04.01.2018
NO04.01.2018
GR05.01.2018
IS04.02.2018
IE12.04.2018
LU12.04.2018
BE30.04.2018
CH30.04.2018
LI30.04.2018
Former [2019/19]AT04.10.2017
CZ04.10.2017
DK04.10.2017
EE04.10.2017
ES04.10.2017
FI04.10.2017
HR04.10.2017
IT04.10.2017
LT04.10.2017
LV04.10.2017
MC04.10.2017
MT04.10.2017
NL04.10.2017
PL04.10.2017
RO04.10.2017
RS04.10.2017
SE04.10.2017
SI04.10.2017
SK04.10.2017
SM04.10.2017
BG04.01.2018
NO04.01.2018
GR05.01.2018
IS04.02.2018
IE12.04.2018
LU12.04.2018
BE30.04.2018
CH30.04.2018
LI30.04.2018
Former [2019/12]AT04.10.2017
CZ04.10.2017
DK04.10.2017
EE04.10.2017
ES04.10.2017
FI04.10.2017
HR04.10.2017
IT04.10.2017
LT04.10.2017
LV04.10.2017
MC04.10.2017
MT04.10.2017
NL04.10.2017
PL04.10.2017
RO04.10.2017
RS04.10.2017
SE04.10.2017
SI04.10.2017
SK04.10.2017
SM04.10.2017
BG04.01.2018
NO04.01.2018
GR05.01.2018
IS04.02.2018
LU12.04.2018
BE30.04.2018
CH30.04.2018
LI30.04.2018
Former [2019/08]AT04.10.2017
CZ04.10.2017
DK04.10.2017
EE04.10.2017
ES04.10.2017
FI04.10.2017
HR04.10.2017
IT04.10.2017
LT04.10.2017
LV04.10.2017
MC04.10.2017
MT04.10.2017
NL04.10.2017
PL04.10.2017
RO04.10.2017
RS04.10.2017
SE04.10.2017
SI04.10.2017
SK04.10.2017
SM04.10.2017
BG04.01.2018
NO04.01.2018
GR05.01.2018
IS04.02.2018
LU12.04.2018
Former [2018/52]AT04.10.2017
CZ04.10.2017
DK04.10.2017
EE04.10.2017
ES04.10.2017
FI04.10.2017
HR04.10.2017
IT04.10.2017
LT04.10.2017
LV04.10.2017
MC04.10.2017
MT04.10.2017
NL04.10.2017
PL04.10.2017
RO04.10.2017
RS04.10.2017
SE04.10.2017
SI04.10.2017
SK04.10.2017
SM04.10.2017
BG04.01.2018
NO04.01.2018
GR05.01.2018
IS04.02.2018
Former [2018/43]AT04.10.2017
CZ04.10.2017
DK04.10.2017
EE04.10.2017
ES04.10.2017
FI04.10.2017
HR04.10.2017
IT04.10.2017
LT04.10.2017
LV04.10.2017
MT04.10.2017
NL04.10.2017
PL04.10.2017
RO04.10.2017
RS04.10.2017
SE04.10.2017
SK04.10.2017
SM04.10.2017
BG04.01.2018
NO04.01.2018
GR05.01.2018
IS04.02.2018
Former [2018/40]AT04.10.2017
CZ04.10.2017
DK04.10.2017
EE04.10.2017
ES04.10.2017
FI04.10.2017
HR04.10.2017
IT04.10.2017
LT04.10.2017
LV04.10.2017
NL04.10.2017
PL04.10.2017
RO04.10.2017
RS04.10.2017
SE04.10.2017
SK04.10.2017
SM04.10.2017
BG04.01.2018
NO04.01.2018
GR05.01.2018
IS04.02.2018
Former [2018/39]AT04.10.2017
CZ04.10.2017
DK04.10.2017
EE04.10.2017
ES04.10.2017
FI04.10.2017
HR04.10.2017
IT04.10.2017
LT04.10.2017
LV04.10.2017
NL04.10.2017
PL04.10.2017
RS04.10.2017
SE04.10.2017
SK04.10.2017
SM04.10.2017
BG04.01.2018
NO04.01.2018
GR05.01.2018
IS04.02.2018
Former [2018/37]AT04.10.2017
CZ04.10.2017
DK04.10.2017
EE04.10.2017
ES04.10.2017
FI04.10.2017
HR04.10.2017
LT04.10.2017
LV04.10.2017
NL04.10.2017
PL04.10.2017
RS04.10.2017
SE04.10.2017
SK04.10.2017
SM04.10.2017
BG04.01.2018
NO04.01.2018
GR05.01.2018
IS04.02.2018
Former [2018/35]AT04.10.2017
CZ04.10.2017
DK04.10.2017
EE04.10.2017
ES04.10.2017
FI04.10.2017
HR04.10.2017
LT04.10.2017
LV04.10.2017
NL04.10.2017
RS04.10.2017
SE04.10.2017
SK04.10.2017
BG04.01.2018
NO04.01.2018
GR05.01.2018
IS04.02.2018
Former [2018/24]AT04.10.2017
ES04.10.2017
FI04.10.2017
HR04.10.2017
LT04.10.2017
LV04.10.2017
NL04.10.2017
RS04.10.2017
SE04.10.2017
BG04.01.2018
NO04.01.2018
GR05.01.2018
IS04.02.2018
Former [2018/22]ES04.10.2017
FI04.10.2017
LT04.10.2017
NL04.10.2017
NO04.01.2018
Former [2018/17]NL04.10.2017
Cited inInternational search[A]EP0911736  (DIGITAL EQUIPMENT CORP [US]) [A] 1-10 * paragraphs [0013] , [0 17] , [0 74] , [ 106] - [0118] - [ 217] - [0219]; figures 2, 6,8,9, 12a *;
 [A]US2003191906  (CHEN WEI-LONG [US], et al) [A] 1-10 * paragraphs [0019] , [0021] , [0027] , [0 28]; figure 2 *;
 [A]US2010049922  (ARONOVICH LIOR [IL], et al) [A] 1-10 * paragraphs [0028] - [0035] - [0066] - [0071] - [0 76] - [0090] - [ 104] , [0116] - [0127] - [ 138]; figures 9, 12; claims 1-5,9, 10, 12 *;
 [A]  - NOEL EISLEY ET AL, "In-Network Cache Coherence", MICROARCHITECTURE, 2006. MICRO-39. 39TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON, IEEE, PI, (20061201), ISBN 978-0-7695-2732-1, pages 321 - 332, XP031034181 [A] 1-10 * the whole document *
 [A]  - THAPAR M ET AL, "Linked list cache coherence for scalable shared memory multiprocessors", PARALLEL PROCESSING SYMPOSIUM, 1993., PROCEEDINGS OF SEVENTH INTERNATI ONAL NEWPORT, CA, USA 13-16 APRIL 1993, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, (19930413), doi:10.1109/IPPS.1993.262852, ISBN 978-0-8186-3442-0, pages 34 - 43, XP010031918 [A] 1-10 * the whole document *

DOI:   http://dx.doi.org/10.1109/IPPS.1993.262852
 [A]  - YUANG ZHANG ET AL, "Towards hierarchical cluster based cache coherence for large-scale network-on-chip", DESIGN&TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCAL ERA, 2009. DTIS '09. 4TH INTERNATIONAL CONFERENCE ON, IEEE, PISCATAWAY, NJ, USA, (20090406), doi:10.1109/DTIS.2009.4938037, ISBN 978-1-4244-4320-8, pages 119 - 122, XP031456362 [A] 1-10 * the whole document *

DOI:   http://dx.doi.org/10.1109/DTIS.2009.4938037
 [A]  - Andreas Lankes, Thomas Wild, Andreas Herkersdorf, "Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in on-chip Networks", 2010 ACM/IEEE International Symposium on Networks-on-Chip (NOCS), doi:10.1109/NOCS.2010.11, ISBN 978-0-7695-4053-5, (20100712), Technishe Universitaet Muenchen, URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5507567, (20130201), XP002691715 [A] 1-10 * the whole document *

DOI:   http://dx.doi.org/10.1109/NOCS.2010.11
by applicant   - THAPAR ET AL., "Linked list cache coherence for scalable shared memory multiprocessors", PROCEEDINGS OF 7TH INTERNATIONAL PARALLEL PROCESSING SYMPOSIUM, (19930413), doi:doi:10.1109/IPPS.1993.262852, pages 34 - 43, XP010031918

DOI:   http://dx.doi.org/10.1109/IPPS.1993.262852
    - YUANG ET AL., "Towards hierarchical cluster based cache coherence for large-scale network-on-chip", PROCEEDING OF 4TH INTERNATIONAL CONFéRENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCAL ERA, (20090406), doi:doi:10.1109/DTIS.2009.4938037, pages 119 - 122, XP031456362

DOI:   http://dx.doi.org/10.1109/DTIS.2009.4938037
    - EISLEY ET AL., "In-network cache coherence", PROCEEDING OF 39TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, (20061209), doi:doi:10.1109/MICRO.2006.27, pages 321 - 332, XP058106989

DOI:   http://dx.doi.org/10.1109/MICRO.2006.27
    - LANKES ET AL., "Comparison of deadlock recovery and avoidance mechanisms to approach message dépendent deadlocks in on-chip networks", PROCEEDING OF 4TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP, (20100503), pages 17 - 24, XP031707271
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