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EP2854172
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EP About this file: EP2854172
| EP2854172 - Method for producing a power semiconductor device with a soldered joint [Right-click to bookmark this link] | Status | The application has been withdrawn Status updated on 18.12.2015 Database last updated on 12.07.2024 | Most recent event Tooltip | 18.12.2015 | Withdrawal of application | published on 20.01.2016 [2016/03] | Applicant(s) | For all designated states SEMIKRON Elektronik GmbH & Co. KG Sigmundstrasse 200 90431 Nürnberg / DE | [2015/14] | Inventor(s) | 01 /
Mohl, Norbert Zwieselweg 15 91189 Regelsbach / DE | [2015/14] | Application number, filing date | 14176900.0 | 14.07.2014 | [2015/14] | Priority number, date | DE201310110812 | 30.09.2013 Original published format: DE102013110812 | [2015/14] | Filing language | DE | Procedural language | DE | Publication | Type: | A2 Application without search report | No.: | EP2854172 | Date: | 01.04.2015 | Language: | DE | [2015/14] | Type: | A3 Search report | No.: | EP2854172 | Date: | 01.07.2015 | Language: | DE | [2015/27] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 29.05.2015 | Classification | IPC: | H01L23/373, H01L23/36, H01L21/48, B23K35/02, B23K35/22, H01L23/498, H01L25/07 | [2015/27] | CPC: |
H01L23/3735 (EP,CN);
B23K35/02 (EP,CN);
B23K35/0222 (EP,CN);
B23K35/0244 (EP,CN);
B23K35/025 (EP,CN);
B23K35/22 (EP,CN);
H01L21/4875 (EP,CN);
H01L23/36 (EP,CN);
H01L24/72 (EP);
H01L2224/48137 (EP,CN);
H01L2224/48227 (EP,CN);
H01L2224/50 (EP,CN);
H01L2224/73269 (EP,CN);
H01L23/49811 (EP,CN);
H01L25/072 (EP,CN);
|
| Former IPC [2015/14] | H01L23/373, H01L23/36, H01L21/48 | Designated contracting states | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR [2015/14] | Extension states | BA | Not yet paid | ME | Not yet paid | Title | German: | Verfahren zur Herstellung einer Leistungshalbleitereinrichtung mit einer Lotverbindung | [2015/14] | English: | Method for producing a power semiconductor device with a soldered joint | [2015/14] | French: | Procédé de fabrication d'un dispositif à semi-conducteurs de puissance doté d'une liaison soudée | [2015/14] | Examination procedure | 14.07.2014 | Examination requested [2015/14] | 15.12.2015 | Application withdrawn by applicant [2016/03] |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [XY]US3900153 (BEERWERTH WOLFGANG, et al) [X] 1,5,7-12 * figure - * * column 2, line 53 - column 4, line 51 * [Y] 2-4,6,13-15; | [XY]JPH03281088 (TAIYO YUDEN KK) [X] 1,5-9,12,14 * abstract * * figure - * [Y] 2-4,10,11,13,15; | [A]US5076485 (MACKAY COLIN A [US]) [A] 14 * figure - * * column 7, line 25 - line 41 *; | [A]JPH06285686 (KANSAI NIPPON ELECTRIC) [A] 1-15 * abstract * * figure - *; | [A]EP0795891 (TECH GMBH ANTRIEBSTECHNIK UND [DE]) [A] 1-15 * figure - * * column 2, line 7 - column 3, line 6 * * column 5, line 41 - line 50 ** claims 14-17 *; | [XA]JP2001168252 (SHIBAFU ENGINEERING KK, et al) [X] 1-3,5-9 * abstract * * figure - * [A] 4,10-15; | [XY]US2005161489 (PIKULSKI JOSEPH L [US]) [X] 1-3,5,7-9,12 * figure - * * paragraph [0015] - paragraph [0020] * * paragraph [0027] - paragraph [0034] * [Y] 4,6,10,11,13-15; | [XA]US2009236725 (HIRANO NAOHIKO [JP], et al) [X] 1 * figure - * * paragraph [0017] * * paragraph [0027] - paragraph [0053] * * paragraph [0064] * [A] 5-9; | [A]WO2010050455 (KYOCERA CORP [JP], et al) [A] 1-15 * abstract * * figure - * | by applicant | DE1226715 | DE102005055713 | DE102010043446 |