blank Quick help
blank Maintenance news

Scheduled maintenance

Regular maintenance outages:
between 05.00 and 05.15 hrs CET (Monday to Sunday).

Other outages
Availability

2022.02.11

More...
blank News flashes

News Flashes

New version of the European Patent Register – SPC proceedings information in the Unitary Patent Register.

2024-07-24

More...
blank Related links

Release notes
European Patent Register Assistant
European Patent Register Resource Book
European Patent Register – pocket guide
FAQ - European Patent Register
FAQ - Register Alert
Federated Register (Flyer)
Global Dossier (Flyer)
Register events
Deep link coverage
Federated Register content
The Patent Information Tour
Fair use charter

Extract from the Register of European Patents

EP About this file: EP2977894

EP2977894 - Creating an FPGA code with automatically inserted influencing structure [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  19.07.2019
Database last updated on 11.09.2024
FormerThe patent has been granted
Status updated on  10.08.2018
FormerGrant of patent is intended
Status updated on  13.06.2018
FormerExamination is in progress
Status updated on  21.12.2016
Most recent event   Tooltip01.07.2022Lapse of the patent in a contracting state
New state(s): MK		published on 03.08.2022  [2022/31]
Applicant(s)For all designated states
dSPACE digital signal processing and control engineering GmbH
Rathenaustraße 26
33102 Paderborn / DE
[2016/04]
Inventor(s)01 / Kalte, Heiko
Germanenstr. 13
33106 Paderborn / DE
02 / Lubeley, Dominik
Hermannsweg 50
33415 Verl / DE
03 / Funke, Lukas
Ferdinandstr. 67
33102 Paderborn / DE
04 / Klahold, Jürgen
Eichenweg 4
33034 Brakel / DE
 [2016/04]
Application number, filing date14177800.121.07.2014
[2016/04]
Filing languageDE
Procedural languageDE
PublicationType: A1 Application with search report 
No.:EP2977894
Date:27.01.2016
Language:DE
[2016/04]
Type: B1 Patent specification 
No.:EP2977894
Date:12.09.2018
Language:DE
[2018/37]
Search report(s)(Supplementary) European search report - dispatched on:EP23.01.2015
ClassificationIPC:G06F8/41, G06F17/50, G06F11/26, G06F11/36
[2018/26]
CPC:
G06F8/423 (EP); G06F30/343 (US); G06F11/3624 (EP);
G06F11/3648 (EP); G06F30/33 (EP); G06F30/34 (EP)
Former IPC [2016/04]G06F9/45, G06F11/36, G06F17/50, G06F11/26
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2016/36]
Former [2016/04]AL,  AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  HR,  HU,  IE,  IS,  IT,  LI,  LT,  LU,  LV,  MC,  MK,  MT,  NL,  NO,  PL,  PT,  RO,  RS,  SE,  SI,  SK,  SM,  TR 
TitleGerman:Erstellen eines FPGA-Codes mit automatisch eingefügter Beeinflussungsstruktur[2016/04]
English:Creating an FPGA code with automatically inserted influencing structure[2016/04]
French:Création d'un code FPGA ayant une structure d'influence automatiquement insérée[2016/04]
Examination procedure29.06.2016Amendment by applicant (claims and/or description)
27.07.2016Examination requested  [2016/36]
25.08.2016Despatch of a communication from the examining division (Time limit: M04)
20.12.2016Reply to a communication from the examining division
14.05.2018Cancellation of oral proceeding that was planned for 31.05.2018
31.05.2018Date of oral proceedings (cancelled)
14.06.2018Communication of intention to grant the patent
17.07.2018Fee for grant paid
17.07.2018Fee for publishing/printing paid
17.07.2018Receipt of the translation of the claim(s)
Opposition(s)13.06.2019No opposition filed within time limit [2019/34]
Fees paidRenewal fee
01.08.2016Renewal fee patent year 03
31.07.2017Renewal fee patent year 04
31.07.2018Renewal fee patent year 05
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipHU21.07.2014
AL12.09.2018
CY12.09.2018
CZ12.09.2018
DK12.09.2018
EE12.09.2018
ES12.09.2018
FI12.09.2018
HR12.09.2018
IT12.09.2018
LT12.09.2018
LV12.09.2018
MC12.09.2018
MK12.09.2018
MT12.09.2018
NL12.09.2018
PL12.09.2018
RO12.09.2018
RS12.09.2018
SE12.09.2018
SI12.09.2018
SK12.09.2018
SM12.09.2018
TR12.09.2018
BG12.12.2018
NO12.12.2018
GR13.12.2018
IS12.01.2019
PT12.01.2019
[2022/31]
Former [2021/34]HU21.07.2014
AL12.09.2018
CY12.09.2018
CZ12.09.2018
DK12.09.2018
EE12.09.2018
ES12.09.2018
FI12.09.2018
HR12.09.2018
IT12.09.2018
LT12.09.2018
LV12.09.2018
MC12.09.2018
MT12.09.2018
NL12.09.2018
PL12.09.2018
RO12.09.2018
RS12.09.2018
SE12.09.2018
SI12.09.2018
SK12.09.2018
SM12.09.2018
TR12.09.2018
BG12.12.2018
NO12.12.2018
GR13.12.2018
IS12.01.2019
PT12.01.2019
Former [2021/32]HU21.07.2014
AL12.09.2018
CY12.09.2018
CZ12.09.2018
DK12.09.2018
EE12.09.2018
ES12.09.2018
FI12.09.2018
HR12.09.2018
IT12.09.2018
LT12.09.2018
LV12.09.2018
MC12.09.2018
NL12.09.2018
PL12.09.2018
RO12.09.2018
RS12.09.2018
SE12.09.2018
SI12.09.2018
SK12.09.2018
SM12.09.2018
TR12.09.2018
BG12.12.2018
NO12.12.2018
GR13.12.2018
IS12.01.2019
PT12.01.2019
Former [2021/26]AL12.09.2018
CY12.09.2018
CZ12.09.2018
DK12.09.2018
EE12.09.2018
ES12.09.2018
FI12.09.2018
HR12.09.2018
IT12.09.2018
LT12.09.2018
LV12.09.2018
MC12.09.2018
NL12.09.2018
PL12.09.2018
RO12.09.2018
RS12.09.2018
SE12.09.2018
SI12.09.2018
SK12.09.2018
SM12.09.2018
TR12.09.2018
BG12.12.2018
NO12.12.2018
GR13.12.2018
IS12.01.2019
PT12.01.2019
Former [2020/17]AL12.09.2018
CZ12.09.2018
DK12.09.2018
EE12.09.2018
ES12.09.2018
FI12.09.2018
HR12.09.2018
IT12.09.2018
LT12.09.2018
LV12.09.2018
MC12.09.2018
NL12.09.2018
PL12.09.2018
RO12.09.2018
RS12.09.2018
SE12.09.2018
SI12.09.2018
SK12.09.2018
SM12.09.2018
TR12.09.2018
BG12.12.2018
NO12.12.2018
GR13.12.2018
IS12.01.2019
PT12.01.2019
Former [2020/14]AL12.09.2018
CZ12.09.2018
DK12.09.2018
EE12.09.2018
ES12.09.2018
FI12.09.2018
HR12.09.2018
IT12.09.2018
LT12.09.2018
LV12.09.2018
MC12.09.2018
NL12.09.2018
PL12.09.2018
RO12.09.2018
RS12.09.2018
SE12.09.2018
SI12.09.2018
SK12.09.2018
SM12.09.2018
BG12.12.2018
NO12.12.2018
GR13.12.2018
IS12.01.2019
PT12.01.2019
Former [2019/37]AL12.09.2018
CZ12.09.2018
DK12.09.2018
EE12.09.2018
ES12.09.2018
FI12.09.2018
HR12.09.2018
IT12.09.2018
LT12.09.2018
LV12.09.2018
NL12.09.2018
PL12.09.2018
RO12.09.2018
RS12.09.2018
SE12.09.2018
SI12.09.2018
SK12.09.2018
SM12.09.2018
BG12.12.2018
NO12.12.2018
GR13.12.2018
IS12.01.2019
PT12.01.2019
Former [2019/34]AL12.09.2018
CZ12.09.2018
DK12.09.2018
EE12.09.2018
ES12.09.2018
FI12.09.2018
HR12.09.2018
IT12.09.2018
LT12.09.2018
LV12.09.2018
NL12.09.2018
PL12.09.2018
RO12.09.2018
RS12.09.2018
SE12.09.2018
SK12.09.2018
SM12.09.2018
BG12.12.2018
NO12.12.2018
GR13.12.2018
IS12.01.2019
PT12.01.2019
Former [2019/26]AL12.09.2018
CZ12.09.2018
EE12.09.2018
ES12.09.2018
FI12.09.2018
HR12.09.2018
IT12.09.2018
LT12.09.2018
LV12.09.2018
NL12.09.2018
PL12.09.2018
RO12.09.2018
RS12.09.2018
SE12.09.2018
SK12.09.2018
SM12.09.2018
BG12.12.2018
NO12.12.2018
GR13.12.2018
IS12.01.2019
PT12.01.2019
Former [2019/23]AL12.09.2018
CZ12.09.2018
EE12.09.2018
ES12.09.2018
FI12.09.2018
HR12.09.2018
IT12.09.2018
LT12.09.2018
LV12.09.2018
NL12.09.2018
PL12.09.2018
RO12.09.2018
RS12.09.2018
SE12.09.2018
SK12.09.2018
BG12.12.2018
NO12.12.2018
GR13.12.2018
IS12.01.2019
Former [2019/22]AL12.09.2018
CZ12.09.2018
FI12.09.2018
HR12.09.2018
IT12.09.2018
LT12.09.2018
LV12.09.2018
NL12.09.2018
PL12.09.2018
RO12.09.2018
RS12.09.2018
SE12.09.2018
BG12.12.2018
NO12.12.2018
GR13.12.2018
IS12.01.2019
Former [2019/21]AL12.09.2018
FI12.09.2018
HR12.09.2018
IT12.09.2018
LT12.09.2018
LV12.09.2018
NL12.09.2018
RS12.09.2018
SE12.09.2018
BG12.12.2018
NO12.12.2018
GR13.12.2018
IS12.01.2019
Former [2019/20]AL12.09.2018
FI12.09.2018
HR12.09.2018
LT12.09.2018
LV12.09.2018
NL12.09.2018
RS12.09.2018
SE12.09.2018
BG12.12.2018
NO12.12.2018
GR13.12.2018
Former [2019/12]AL12.09.2018
FI12.09.2018
HR12.09.2018
LT12.09.2018
LV12.09.2018
RS12.09.2018
SE12.09.2018
BG12.12.2018
NO12.12.2018
GR13.12.2018
Former [2019/11]FI12.09.2018
HR12.09.2018
LT12.09.2018
RS12.09.2018
SE12.09.2018
BG12.12.2018
NO12.12.2018
GR13.12.2018
Former [2019/10]FI12.09.2018
LT12.09.2018
RS12.09.2018
SE12.09.2018
BG12.12.2018
NO12.12.2018
GR13.12.2018
Former [2019/08]FI12.09.2018
LT12.09.2018
NO12.12.2018
Former [2019/07]LT12.09.2018
Documents cited:Search[Y]US7458042  (COLLE PIERRE [FR], et al) [Y] 1,7,9-15 * column 4 * * column 6 * * column 7 *;
 [Y]US2009307667  (BOOTH ALAN E [US], et al) [Y] 1,7,9-15 * paragraph [0024] * * paragraph [0031] *;
 [XI]US2012005547  (CHANG CHIOUMIN M [US], et al) [X] 1,6-11,13-15 * paragraph [0040] * * paragraph [0042] * [I] 2-5,12;
 [A]  - GRAHAM P ET AL, "Instrumenting Bitstreams for Debugging FPGA Circuits", FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, 2001. FCCM '01. THE 9TH ANNUAL IEEE SYMPOSIUM ON ROHNERT PARK, CA, USA 29-02 APRIL 2001, PISCATAWAY, NJ, USA,IEEE, (20010429), ISBN 978-0-7695-2667-6, pages 41 - 50, XP010789103 [A] 1-15 * section 3.2 *
 [A]  - LAGADEC L ET AL, "Software-like debugging methodology for reconfigurable platforms", PARALLEL&DISTRIBUTED PROCESSING, 2009. IPDPS 2009. IEEE INTERNATIONAL SYMPOSIUM ON, IEEE, PISCATAWAY, NJ, USA, (20090523), ISBN 978-1-4244-3751-1, pages 1 - 4, XP031487669 [A] 1-15 * the whole document *
Examination   - Anonymous, "Field-programmable gate array - Wikipedia, the free encyclopedia", (20130204), URL: http://en.wikipedia.org/w/index.php?title=Field-programmable_gate_array&oldid=536512233, (20140613), XP055123299
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.