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EP2871589
European procedure
Extract from the Register of European Patents
EP About this file: EP2871589
| EP2871589 - Method and system for generating a circuit description for a multi-die field-programmable gate array [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 03.07.2020 Database last updated on 18.11.2024 | |
| Former | The patent has been granted Status updated on 24.05.2019 | ||
| Former | Grant of patent is intended Status updated on 06.03.2019 | ||
| Former | Examination is in progress Status updated on 28.09.2018 | Most recent event Tooltip | 01.07.2022 | Lapse of the patent in a contracting state New state(s): MK | published on 03.08.2022 [2022/31] | Applicant(s) | For all designated states Synopsys, Inc. 690 East Middlefield Road Mountain View, CA 94043 / US | [2019/26] |
| Former [2019/14] | For all designated states Synopsys, Inc. 700 East Middlefield Road Mountain View, CA 94043 / US | ||
| Former [2015/20] | For all designated states Synopsys, Inc. 700 E. Middlefield Road Mountain View, CA 94043 / US | Inventor(s) | 01 /
Emirian, Frederic 28 Avenue de la Division Leclerc 92160 Antony / FR | [2015/20] | Representative(s) | Epping - Hermann - Fischer Patentanwaltsgesellschaft mbH Schloßschmidstraße 5 80639 München / DE | [2015/20] | Application number, filing date | 14189043.4 | 15.10.2014 | [2015/20] | Priority number, date | EP20130192140 | 08.11.2013 Original published format: EP 13192140 | [2015/20] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP2871589 | Date: | 13.05.2015 | Language: | EN | [2015/20] | Type: | B1 Patent specification | No.: | EP2871589 | Date: | 26.06.2019 | Language: | EN | [2019/26] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 20.03.2015 | Classification | IPC: | G06F17/50 | [2015/20] | CPC: |
G06F30/331 (EP,US);
G06F30/347 (US);
G06F30/327 (US);
G06F30/34 (EP,US);
G06F30/392 (US);
G06F30/398 (US)
| Designated contracting states | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR [2015/52] |
| Former [2015/20] | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR | Title | German: | Verfahren und System zur Erzeugung einer Schaltungsbeschreibung für ein feldprogrammierbares Gate-Array mit mehreren Matrizen | [2015/20] | English: | Method and system for generating a circuit description for a multi-die field-programmable gate array | [2015/20] | French: | Procédé et système de génération d'une description de circuit pour un réseau de portes programmable par l'utilisateur à puces multiples | [2015/20] | Examination procedure | 13.11.2015 | Amendment by applicant (claims and/or description) | 13.11.2015 | Examination requested [2015/52] | 28.09.2018 | Despatch of a communication from the examining division (Time limit: M04) | 28.01.2019 | Reply to a communication from the examining division | 07.03.2019 | Communication of intention to grant the patent | 15.05.2019 | Fee for grant paid | 15.05.2019 | Fee for publishing/printing paid | 15.05.2019 | Receipt of the translation of the claim(s) | Opposition(s) | 03.06.2020 | No opposition filed within time limit [2020/32] | Fees paid | Renewal fee | 11.10.2016 | Renewal fee patent year 03 | 11.10.2017 | Renewal fee patent year 04 | 11.10.2018 | Renewal fee patent year 05 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
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| NO | 26.09.2019 | Documents cited: | Search | [I]WO9423389 (MASSACHUSETTS INST TECHNOLOGY [US], et al) [I] 1-13 * page 2 - page 5; figures 3,4 ** page 8, line 20 - page 9, line 15 *; | [I] - Kirk Saban, "Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency", (20121211), URL: http://www.xilinx.com/support/documentation/white_papers/wp380_Stacked_Silicon_Interconnect_Technology.pdf, (20150302), XP055172904 [I] 1-13 * page 4 * * page 7 - page 8 * |