| EP3026711 - IMPROVED METHOD FOR INDUCING STRAIN IN A TRANSISTOR CHANNEL USING SACRIFICIAL SOURCE/DRAIN REGIONS AND A GATE REPLACEMENT [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 30.10.2020 Database last updated on 28.03.2026 | |
| Former | The patent has been granted Status updated on 22.11.2019 | ||
| Former | Grant of patent is intended Status updated on 01.05.2019 | Most recent event Tooltip | 08.07.2022 | Lapse of the patent in a contracting state New state(s): MK | published on 10.08.2022 [2022/32] | Applicant(s) | For all designated states Commissariat à l'Énergie Atomique et aux Énergies Alternatives 25, rue Leblanc Bâtiment "le Ponant D" 75015 Paris / FR | For all designated states STMicroelectronics, Inc. 750 Canyon Drive, Suite 300 Coppell, TX 75019 / US | [2016/22] | Inventor(s) | 01 /
REBOH, Shay 17, rue des Martyrs 38054 Grenoble / FR | 02 /
MORIN, Pierre 215 Milner Avenue Albany, NY New York 12208 / US | [2019/52] |
| Former [2016/24] | 01 /
REBOH, Shay 17, rue des Martyrs 38054 Grenoble / FR | ||
| 02 /
MORIN, Pierre 215 Milner Avenue ALBANY, NY New York 12208 / US | Representative(s) | Brevalex Tour Trinity 1 B Place de la Défense 92400 Courbevoie / FR | [N/P] |
| Former [2016/22] | Brevalex 95, rue d'Amsterdam 75378 Paris Cedex 8 / FR | Application number, filing date | 15196134.9 | 24.11.2015 | [2016/22] | Priority number, date | FR20140061459 | 25.11.2014 Original published format: FR 1461459 | [2016/22] | Filing language | FR | Procedural language | FR | Publication | Type: | A1 Application with search report | No.: | EP3026711 | Date: | 01.06.2016 | Language: | FR | [2016/22] | Type: | B1 Patent specification | No.: | EP3026711 | Date: | 25.12.2019 | Language: | FR | [2019/52] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 12.04.2016 | Classification | IPC: | H01L21/336, H01L29/165, H01L29/78 | [2019/20] | CPC: |
H10D30/797 (EP,US);
H10D30/0275 (EP,US);
H10D62/021 (EP,US);
H10D62/115 (US);
H10D62/822 (EP,US);
H10D62/832 (US);
|
| Former IPC [2016/22] | H01L29/66, H01L29/165, H01L29/78 | Designated contracting states | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR [2016/46] |
| Former [2016/22] | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR | Title | German: | VERBESSERTES VERFAHREN ZUR ERZEUGUNG EINER DEHNUNG IN EINEM TRANSISTORKANAL MITHILFE VON OPFER-SOURCE- UND OPFER-DRAIN-SCHICHTEN UND EINEM GATE-AUSTAUSCH | [2019/20] | English: | IMPROVED METHOD FOR INDUCING STRAIN IN A TRANSISTOR CHANNEL USING SACRIFICIAL SOURCE/DRAIN REGIONS AND A GATE REPLACEMENT | [2016/22] | French: | PROCEDE AMELIORE POUR INDUIRE UNE CONTRAINTE DANS UN CANAL DE TRANSISTOR A L'AIDE DE REGIONS SOURCE/DRAIN SACRIFICIELLES ET D'UN REMPLACEMENT DE GRILLE | [2016/22] |
| Former [2016/22] | VERBESSERTES VERFAHREN ZUR INDUKTION EINER SPANNUNG IN EINEM TRANSISTORKANAL MITHILFE VON OPFER-SOURCE- UND OPFER-DRAIN-SCHICHTEN UND EINEM GATE-WECHSEL | Examination procedure | 06.10.2016 | Amendment by applicant (claims and/or description) | 06.10.2016 | Examination requested [2016/46] | 02.05.2019 | Communication of intention to grant the patent | 30.08.2019 | Fee for grant paid | 30.08.2019 | Fee for publishing/printing paid | 30.08.2019 | Receipt of the translation of the claim(s) | Opposition(s) | 28.09.2020 | No opposition filed within time limit [2020/49] | Fees paid | Renewal fee | 24.10.2017 | Renewal fee patent year 03 | 25.10.2018 | Renewal fee patent year 04 | 25.10.2019 | Renewal fee patent year 05 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | HU | 24.11.2015 | AL | 25.12.2019 | AT | 25.12.2019 | CY | 25.12.2019 | CZ | 25.12.2019 | DK | 25.12.2019 | EE | 25.12.2019 | ES | 25.12.2019 | FI | 25.12.2019 | HR | 25.12.2019 | LT | 25.12.2019 | LV | 25.12.2019 | MC | 25.12.2019 | MK | 25.12.2019 | MT | 25.12.2019 | NL | 25.12.2019 | PL | 25.12.2019 | RO | 25.12.2019 | RS | 25.12.2019 | SE | 25.12.2019 | SI | 25.12.2019 | SK | 25.12.2019 | SM | 25.12.2019 | TR | 25.12.2019 | BG | 25.03.2020 | NO | 25.03.2020 | GR | 26.03.2020 | IS | 25.04.2020 | PT | 20.05.2020 | [2022/32] |
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| Former [2020/21] | NO | 25.03.2020 | Documents cited: | Search | [A] US2012302019 (CHENG KANGGUO et al.) | [A] US2009321843 (WAITE ANDREW et al.) | [A] US2005090066 (ZHU HUILONG et al.) [A] 1-18 * paragraph [0001] - paragraph [0046]; figures 1-14 * | [A] US2011269278 (HOENTSCHEL JAN et al.) [A] 1-18 * paragraph [0027] - paragraph [0045]; figures 1a-1j * | by applicant | SCOTT E. THOMPSON ET AL.: "A Logic Nanotechnology Featuring Strained-Silicon", IEEE ELECTRON DEVICE LETTERS, vol. 25, no. 4, April 2004 (2004-04-01), pages 191 | PETER VERHEYEN ET AL.: "Strain Enhanced NMOS Using In Situ Doped Embedded $i1-xCx S/D Stressors With up to 1.5% Substitutional Carbon Content Grown Using a Novel Deposition Process", IEEE ELECTRON DEVICE LETTERS, vol. 29, no. 11, November 2008 (2008-11-01) |