EP3373304 - SEMICONDUCTOR CELL FOR PERFORMING A LOGIC XNOR OR XOR OPERATION [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 11.10.2019 Database last updated on 03.09.2024 | |
Former | The application has been published Status updated on 10.08.2018 | Most recent event Tooltip | 11.10.2019 | Application deemed to be withdrawn | published on 13.11.2019 [2019/46] | Applicant(s) | For all designated states IMEC vzw Kapeldreef 75 3001 Leuven / BE | For all designated states Katholieke Universiteit Leuven K.U. Leuven R&D Waaistraat 6 Box 5105 3000 Leuven / BE | [2018/37] | Inventor(s) | 01 /
GARBIN, Daniele C/O IMEC VZW, Patent Department Kapeldreef 75 3001 Leuven / BE | 02 /
RODOPOULOS, Dimitrios C/O IMEC VZW, Patent Department Kapeldreef 75 3001 Leuven / BE | 03 /
DEBACKER, Peter c/o IMEC VZW, Patent department Kapeldreef 75 3001 Leuven / BE | 04 /
RAGHAVAN, Praveen c/o IMEC VZW, patent department Kapeldreef 75 3001 Leuven / BE | [2018/37] | Representative(s) | Winger Hundelgemsesteenweg 1116 9820 Merelbeke / BE | [N/P] |
Former [2018/37] | DenK iP Hundelgemsesteenweg 1116 9820 Merelbeke / BE | Application number, filing date | 17202762.5 | 21.11.2017 | [2018/37] | Priority number, date | EP20160199877 | 21.11.2016 Original published format: EP 16199877 | [2018/37] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP3373304 | Date: | 12.09.2018 | Language: | EN | [2018/37] | Type: | A3 Search report | No.: | EP3373304 | Date: | 05.12.2018 | Language: | EN | [2018/49] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 07.11.2018 | Classification | IPC: | G11C11/54, G11C11/16, G11C13/00, H03K19/168, G06N3/063, G06N3/04 | [2018/37] | CPC: |
G06N3/063 (EP,US);
G06N3/04 (US);
G06N3/045 (EP,US);
G11C11/1659 (EP,US);
G11C11/54 (EP,US);
G11C13/003 (EP,US);
| Designated contracting states | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR [2018/37] | Extension states | BA | Not yet paid | ME | Not yet paid | Validation states | MA | Not yet paid | MD | Not yet paid | Title | German: | HALBLEITERZELLE ZUR AUSFÜHRUNG EINER LOGISCHEN XNOR- ODER XNOR-OPERATION | [2018/37] | English: | SEMICONDUCTOR CELL FOR PERFORMING A LOGIC XNOR OR XOR OPERATION | [2018/37] | French: | CELLULE À SEMI-CONDUCTEUR PERMETTANT DE RÉALISER UNE OPÉRATION XNOR OU XOR | [2018/37] | Examination procedure | 06.06.2019 | Application deemed to be withdrawn, date of legal effect [2019/46] | 21.06.2019 | Despatch of communication that the application is deemed to be withdrawn, reason: examination fee not paid in time [2019/46] |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [XYI]US4999525 (PARK CHIN S [US], et al) [X] 1,2,4,6,8,12,14 * column 3, lines 9-25; figures 4-5 * * columns 7-9 * * claim 8 * [Y] 5 [I] 7,9,10,13,15; | [XI]US5258946 (GRAF HANS P [US]) [X] 1-3,6,8,12,14 * column 5, lines 22-39; figures 1-2 * [I] 7,9,10,13,15; | [Y]US2003146469 (MATSUOKA HIDEYUKI [JP], et al) [Y] 5 * paragraph [0009]; figure 1 *; | [XY]US2006067097 (LIEN CHUEN-DER [US], et al) [X] 1-4,6,8 * paragraphs [0010] , [0 30] , [0070] - [0080] - [0 84] - [0089]; figures 5C-5D, 6 * [Y] 5,11-15; | [Y]US2007008773 (SCHEUERLEIN ROY E [US]) [Y] 11* figures 6a,7 *; | [XYI]US2011051485 (CHANG LELAND [US], et al) [X] 1,2,4,6,8 * paragraphs [0005] , [0015] - [0028]; figures 1-2 * [Y] 5,11-15 [I] 3; | [Y] - Hirokinakahara, "ComputerSystem1: A Deep Neural Network on an FPGA", (20161024), URL: www.ocw.titech.ac.jp, (20180720), XP055494179 [Y] 12-15 * pages 17,24,25 * * pages 28,30-31 * | [Y] - Mohammad Rastegari ET AL, "XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks", Medical image computing and computer-assisted intervention - MICCAI 2015 : 18th international conference, Munich, Germany, October 5-9, 2015; proceedings, Cham, Springer International Publishing, (20160802), vol. 9908, pages 525 - 542, 032548, doi:10.1007/978-3-319-46493-0_32, ISSN 0302-9743, ISBN 978-3-642-40759-8, XP055405845 [Y] 13 * figures 1,2 * DOI: http://dx.doi.org/10.1007/978-3-319-46493-0_32 | [T] - SUN XIAOYU ET AL, "XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks", 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), EDAA, (20180319), doi:10.23919/DATE.2018.8342235, pages 1423 - 1428, XP033334079 [T] 1-4,6-10,12-15 * page 1424; figure 1 * * page 1425 * DOI: http://dx.doi.org/10.23919/DATE.2018.8342235 | [T] - Amogh Agrawal ET AL, "Xcel-RAM: Accelerating Binary Neural Networks in High-Throughput SRAM Compute Arrays", (20181022), URL: https://arxiv.org/pdf/1807.00343.pdf, (20181025), XP055519171 [T] 1-4,6-10,12-15 * figures 2,6 * | by applicant | - COURBARIAUX et al., CoRR, (20160000), URL: https://arxiv.org/abs/1602.02830 |