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EP3513293
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EP Citations: EP3513293
| Cited in | Search | Type: | Patent literature | Publication No.: | US4924467
[A] (CRISWELL PETER B [US]) [A] 1-12 * abstract * * column 2, lines 21-54 * * column 2, line 66 - column 3, line 15 * * column 3, line 27 - column 4, line 14 ** column 5, line 12 - column 7, line 30 *; | Type: | Non-patent literature | Publication information: | [I] - M. D. Sika ET AL, "Applying Residue Arithmetic Codes to Combinational Logic to Reduce Single Event Upsets", (20140416), URL: https://www.cc.gatech.edu/-ayazdanb/pubtication/papers/residue-radecs13.pdf, (20180806), XP055497557 [I] 1-12 * abstract * * page 1 - page 2 * | Cited in | International search | Type: | Patent literature | Publication No.: | US6963217
[A] (SAMUDRALA PRAVEEN K [US], et al) [A] 1-20 * entire document *; | Type: | Patent literature | Publication No.: | US7036059
[A] (CARMICHAEL CARL H [US], et al) [A] 1-20 * entire document *; | Type: | Patent literature | Publication No.: | US7035891
[A] (MAKINENI SIVAKUMAR [US], et al) [A] 1-20 * entire document *; | Type: | Patent literature | Publication No.: | US7260742
[A] (CZAJKOWSKI DAVID R [US]) [A] 1-20 * entire document *; | Type: | Patent literature | Publication No.: | US2011013768
[A] (LAMBERT ROBERT JOHN [CA]) [A] 1-20* entire document *; | Type: | Patent literature | Publication No.: | US8489919
[A] (CLARK LAWRENCE T [US], et al) [A] 1-20 * (col. 1, In 30-33; col. 4, In 17-23; col. 12, In 58; col. 17, In 61-62) *; | Type: | Patent literature | Publication No.: | US2015277855
[A] (SHIN JONGHOON [KR], et al) [A] 1-20 * entire document *; | Type: | Non-patent literature | Publication information: | [A] - SIKA, M. D. et al., "Applying Residue Arithmetic Codes to Combinational Logic to Reduce Single Event Upsets", (20140416), URL: https://www.cc.gatech.edu/-ayazdanb/pubtication/papers/residue-radecs13.pdf, (20171113), XP055497557 [A] 1-20 * (pg. 1, col. 1 and col. 2; pg. 2, col. 1 and col. 2 ; pg. 3, col. 1; pg. 4, col. 2; Fig. 1, Fig. 2). * | Type: | Non-patent literature | Publication information: | [A] - BOLCHINI et al., "TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs", Defect and Fault-Tolerance in VLSI Systems , 2007. DFT'07. 22nd IEEE International Symposium, (20070000), URL: https://pdfs.semanticscholar.org/f6f4/8adba7b71a93cb4b1d591f051a6c9dd37c5e.pdf, (20171113), XP031337801 [A] 1-20 * entire document * | Type: | Non-patent literature | Publication information: | [A] - SIKA, MICHEL D. et al., Low Energy Hardening of Combinatorial Logic using Standard Cells and Residue Codes, (20140416), URL: https://www.cc.gatech.edu/-ayazdanb/ publication/papers/residue-gomactech14pdf, (20171113), XP055497559 [A] 1-20 * entire document * | Type: | Non-patent literature | Publication information: | [L] - Index of /~ayazdanb/publication/papers, URL: https://www.cc.gatech.edu/-ayazdanb/publication/papers, (20171113) [L] 1-20 * (cites publication dates for both Sika references) * | Cited in | by applicant | Type: | Patent literature | Publication No.: | US4924467
| Type: | Non-patent literature | Publication information: | - M.D. SIKA, Applying Residue Arithmetic Codes to Combinational Logic to Reduce Single Event Upsets |