Extract from the Register of European Patents

EP About this file: EP3607656

EP3607656 - METHOD AND APPARATUS FOR REDUCING IMPACT OF TRANSISTOR RANDOM MISMATCH IN CIRCUITS [Right-click to bookmark this link]
StatusThe application has been refused
Status updated on  07.03.2025
Database last updated on 28.03.2026
FormerExamination is in progress
Status updated on  20.05.2022
FormerRequest for examination was made
Status updated on  10.01.2020
FormerThe international publication has been made
Status updated on  13.10.2018
Most recent event   Tooltip07.03.2025Refusal of applicationpublished on 09.04.2025  [2025/15]
Applicant(s)For all designated states
Micron Technology, Inc.
8000 South Federal Way
Boise, ID 83716-9632 / US
[2020/07]
Inventor(s)01 / PAN, Dong
6530 E Signal Rock Dr
Boise Idaho 83716 / US
02 / PORTER, John, D.
2756 S Perrault Way
Boise, Idaho 83716 / US
 [2020/26]
Former [2020/07]01 / PAN, Dong
6530 E Signal Rock Dr
Boise Idaho 83716 / US
02 / PORTER, John, D.
12298 W. Oldham Ct
Boise Idaho 83709 / US
Representative(s)Marks & Clerk LLP
15 Fetter Lane
London EC4A 1BW / GB
[N/P]
Former [2020/07]Granleese, Rhian Jane
Marks & Clerk LLP
15 Fetter Lane
London EC4A 1BW / GB
Application number, filing date18780552.806.04.2018
[2020/07]
WO2018US26511
Priority number, dateUS20171548202007.04.2017         Original published format: US201715482020
[2020/07]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report
No.:WO2018187721
Date:11.10.2018
Language:EN
[2018/41]
Type: A1 Application with search report 
No.:EP3607656
Date:12.02.2020
Language:EN
The application published by WIPO in one of the EPO official languages on 11.10.2018 takes the place of the publication of the European patent application.
[2020/07]
Search report(s)International search report - published on:KR11.10.2018
(Supplementary) European search report - dispatched on:EP12.11.2020
ClassificationIPC:H03F3/45, H03M1/10, H03F3/393, // H03M1/06, H03M1/12, H03M1/66
[2020/51]
CPC:
H03F3/393 (EP); H03F3/45183 (KR); H03K5/007 (US);
H03F3/45475 (EP,KR,US); H03F3/45977 (EP,US); H03F3/45995 (EP,US);
H03K17/161 (US); H03K5/1565 (US); H03M1/10 (KR);
H03M3/00 (US); H03F2200/27 (EP); H03F2200/421 (EP);
H03F2203/45044 (EP); H03F2203/45171 (EP); H03F2203/45212 (EP,US);
H03F2203/45226 (EP); H03F2203/45614 (EP); H03F2203/45724 (EP);
H03M1/0607 (EP); H03M1/12 (EP); H03M1/66 (EP) (-)
Former IPC [2020/07]H03F3/45, H03M1/10
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2020/07]
TitleGerman:VERFAHREN UND VORRICHTUNG ZUR VERRINGERUNG DER AUSWIRKUNG VON ZUFÄLLIGEN DISKREPANZEN EINES TRANSISTORS BEI SCHALTUNGEN[2020/07]
English:METHOD AND APPARATUS FOR REDUCING IMPACT OF TRANSISTOR RANDOM MISMATCH IN CIRCUITS[2020/07]
French:PROCÉDÉ ET APPAREIL PERMETTANT DE RÉDUIRE L'IMPACT D'UNE DÉSADAPTATION ALÉATOIRE DE TRANSISTOR DANS DES CIRCUITS[2020/07]
Entry into regional phase07.11.2019National basic fee paid 
07.11.2019Search fee paid 
07.11.2019Designation fee(s) paid 
07.11.2019Examination fee paid 
Examination procedure07.11.2019Examination requested  [2020/07]
11.06.2021Amendment by applicant (claims and/or description)
19.05.2022Despatch of a communication from the examining division (Time limit: M04)
29.09.2022Reply to a communication from the examining division
30.10.2024Application refused, date of legal effect [2025/15]
30.10.2024Date of oral proceedings
02.12.2024Minutes of oral proceedings despatched
03.12.2024Despatch of communication that the application is refused, reason: substantive examination [2025/15]
Fees paidRenewal fee
07.11.2019Renewal fee patent year 03
26.04.2021Renewal fee patent year 04
07.03.2022Renewal fee patent year 05
31.03.2023Renewal fee patent year 06
25.03.2024Renewal fee patent year 07
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Documents cited:Search[XI] US2014354351  (KAWLE ABHILASHA et al.) [X] 1-5,11-15 * figures 2-7 * * paragraphs [0005] - [0034] *[I] 6-10
 [XI]   CHRISTIAN C ENZ ET AL: "Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization", PROCEEDINGS OF THE IEEE., vol. 84, no. 11, 1 September 1996 (1996-09-01), US, pages 1584 - 1614, XP055386680, ISSN: 0018-9219, DOI: 10.1109/5.542410 [X] 1-5,11-15 * figures 10,15 * * page 1590, right-hand column, line 3 - page 1594, left-hand column, line 35 *[I] 6-10

DOI:   http://dx.doi.org/10.1109/5.542410
International search[A] US7236117  (VARMA SEEMA et al.) [A] 1-20 * See column 4, line 9 - column 5, line 58; column 7, line 55 - column 8, line 16; claims 1, 14; and figures 1-5. *
 [A] US2011006831  (PAN DONG et al.) [A] 1-20 * See paragraph [0019]; and figure 2. *
 [A] US2013127526  (SAYUK MARK et al.) [A] 1-20 * See paragraph [0054]; and figure 8. *
 [A] US2012161991  (ZHANG BO et al.) [A] 1-20 * See paragraph [0021]; and figure 1. *
 [A] US7394309  (POTANIN VLADISLAV et al.) [A] 1-20 * See column 3, line 66 - column 4, line 21; and figure 3. *
ExaminationUS9306589
 EP2173031
 US7358876
   FRAISSE CHRISTIAN ET AL: "A [Sigma][Delta] sense chain using chopped integrators for ultra-low-noise MEMS system", ESSCIRC CONFERENCE 2016: 42ND EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, IEEE, 12 September 2016 (2016-09-12), pages 153 - 156, XP032980831, DOI: 10.1109/ESSCIRC.2016.7598265 [I] 6-10

DOI:   http://dx.doi.org/10.1109/ESSCIRC.2016.7598265
by applicantUS201715482020
 US2014354351
   CHRISTIAN C. ENZ ET AL.: "Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization", PROCEEDINGS OF THE IEEE, vol. 84, no. 11, 1996, pages 1584 - 1614, XP055386680, DOI: 10.1109/5.542410

DOI:   http://dx.doi.org/10.1109/5.542410
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