EP3599722 - HIGH LINEARITY DIGITAL-TO-ANALOG CONVERTER WITH ISI-SUPPRESSING METHOD [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 19.08.2022 Database last updated on 16.09.2024 | |
Former | The patent has been granted Status updated on 10.09.2021 | ||
Former | Grant of patent is intended Status updated on 02.05.2021 | ||
Former | Request for examination was made Status updated on 31.07.2020 | ||
Former | The application has been published Status updated on 27.12.2019 | Most recent event Tooltip | 14.06.2024 | Lapse of the patent in a contracting state New state(s): TR | published on 17.07.2024 [2024/29] | Applicant(s) | For all designated states MediaTek Inc. No. 1, Dusing Rd. 1st Science-Based Industrial Park Hsin-Chu 300 / TW | [2020/05] | Inventor(s) | 01 /
HSIAO, Chuan-Hung No.1, Dusing Rd. 1st, Science-Based Industrial Park 30078 Hsin-Chu / TW | 02 /
WEN, Sung-Han No.1, Dusing 1st Rd., Hsinchu Science Park 30078 Hsinchu City / TW | 03 /
CHEN, Kuan-Ta No.1, Dusing 1st Rd., Hsinchu Science Park 30078 Hsinchu City / TW | [2021/41] |
Former [2020/05] | 01 /
HSIAO, Chuan-Hung No.1, Dusing Rd. 1st, Science-Based Industrial Park 30078 Hsin-Chu / TW | ||
02 /
WEN, Sung-Han No.1, Dusing Rd. 1st, Science-Based Industrial Park 30078 Hsin-Chu / TW | |||
03 /
CHEN, Kuan-Ta No.1, Dusing Rd. 1st, Science-Based Industrial Park 30078 Hsin-Chu / TW | Representative(s) | Haseltine Lake Kempner LLP Cheapside House 138 Cheapside London EC2V 6BJ / GB | [2021/41] |
Former [2020/05] | Haseltine Lake Kempner LLP Lincoln House, 5th Floor 300 High Holborn London WC1V 7JH / GB | Application number, filing date | 19187594.7 | 22.07.2019 | [2020/05] | Priority number, date | US201862701885P | 23.07.2018 Original published format: US 201862701885 P | US201916515056 | 18.07.2019 Original published format: US201916515056 | [2020/05] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP3599722 | Date: | 29.01.2020 | Language: | EN | [2020/05] | Type: | B1 Patent specification | No.: | EP3599722 | Date: | 13.10.2021 | Language: | EN | [2021/41] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 17.12.2019 | Classification | IPC: | H03M1/06, H03M1/68, H03M7/36 | [2020/05] | CPC: |
H03M1/0665 (EP,US);
H03M1/662 (CN);
H03M1/687 (US);
H03M1/06 (CN);
H03M1/0668 (EP,US);
H03M1/067 (EP,US);
| Designated contracting states | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR [2020/36] |
Former [2020/05] | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR | Title | German: | DIGITAL/ANALOG-WANDLER MIT HOHER LINEARITÄT UND ISI-UNTERDRÜCKUNGSVERFAHREN | [2020/05] | English: | HIGH LINEARITY DIGITAL-TO-ANALOG CONVERTER WITH ISI-SUPPRESSING METHOD | [2020/05] | French: | CONVERTISSEUR NUMÉRIQUE-ANALOGIQUE À HAUTE LINÉARITÉ COMPORTANT UN PROCÉDÉ DE SUPPRESSION D'ISI | [2020/05] | Examination procedure | 16.06.2020 | Amendment by applicant (claims and/or description) | 26.07.2020 | Examination requested [2020/36] | 26.07.2020 | Date on which the examining division has become responsible | 03.05.2021 | Communication of intention to grant the patent | 03.09.2021 | Fee for grant paid | 03.09.2021 | Fee for publishing/printing paid | 03.09.2021 | Receipt of the translation of the claim(s) | Opposition(s) | 14.07.2022 | No opposition filed within time limit [2022/38] | Fees paid | Renewal fee | 30.07.2021 | Renewal fee patent year 03 |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | HU | 22.07.2019 | AL | 13.10.2021 | AT | 13.10.2021 | CY | 13.10.2021 | CZ | 13.10.2021 | DK | 13.10.2021 | EE | 13.10.2021 | ES | 13.10.2021 | FI | 13.10.2021 | HR | 13.10.2021 | IT | 13.10.2021 | LT | 13.10.2021 | LV | 13.10.2021 | MC | 13.10.2021 | MK | 13.10.2021 | NL | 13.10.2021 | PL | 13.10.2021 | RO | 13.10.2021 | RS | 13.10.2021 | SE | 13.10.2021 | SI | 13.10.2021 | SK | 13.10.2021 | SM | 13.10.2021 | TR | 13.10.2021 | BG | 13.01.2022 | NO | 13.01.2022 | GR | 14.01.2022 | IS | 13.02.2022 | PT | 14.02.2022 | [2024/29] |
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BG | 13.01.2022 | ||
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IS | 13.02.2022 | ||
PT | 14.02.2022 | ||
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BG | 13.01.2022 | ||
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Former [2022/19] | BG | 13.01.2022 | Documents cited: | Search | [XI]EP3288186 (MEDIATEK INC [TW]) [X] 1,9 * paragraphs [0065] , [0067]; figure 16 * [I] 2-5,10-13; | [XI] - R Adams ET AL, "A 113-dB SNR oversampling DAC with segmented noise-shaped scrambling", IEEE Journal of Solid-State Circuits, doi:10.1109/4.735526, (19981212), pages 1871 - 1878, URL: http://ieeexplore.ieee.org/ielx4/4/15831/00735526.pdf?tp=&arnumber=735526&isnumber=15831, (20160628), XP055284296 [X] 1,9 * page 1874, column r, paragraph 2 - page 1875, column l, paragraph 1; figure 10 * [I] 2-5,10-13 DOI: http://dx.doi.org/10.1109/4.735526 | [A] - VAN TUIJL E ET AL, "20.5 - A 128f/sub s/ Multi-Bit /spl Sigma//spl Delta/ CMOS Audio DAC with Real-Time DEM and 115dB SFDR", SOLID-STATE CIRCUITS CONFERENCE, 2004. DIGEST OF TECHNICAL PAPERS. ISSCC. 2004 IEEE INTERNATIONAL, IEEE, PISCATAWAY, NJ, USA, (20040215), doi:10.1109/ISSCC.2004.1332747, ISBN 978-0-7803-8267-1, pages 368 - 375, XP010722306 [A] 5-8,13-15 * page 1, column l, paragraph 1 - paragraph 2; figures 20.5.1,20.5.2 * DOI: http://dx.doi.org/10.1109/ISSCC.2004.1332747 |