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Extract from the Register of European Patents

EP About this file: EP3599722

EP3599722 - HIGH LINEARITY DIGITAL-TO-ANALOG CONVERTER WITH ISI-SUPPRESSING METHOD [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  19.08.2022
Database last updated on 16.09.2024
FormerThe patent has been granted
Status updated on  10.09.2021
FormerGrant of patent is intended
Status updated on  02.05.2021
FormerRequest for examination was made
Status updated on  31.07.2020
FormerThe application has been published
Status updated on  27.12.2019
Most recent event   Tooltip14.06.2024Lapse of the patent in a contracting state
New state(s): TR
published on 17.07.2024  [2024/29]
Applicant(s)For all designated states
MediaTek Inc.
No. 1, Dusing Rd. 1st
Science-Based Industrial Park
Hsin-Chu 300 / TW
[2020/05]
Inventor(s)01 / HSIAO, Chuan-Hung
No.1, Dusing Rd. 1st, Science-Based Industrial
Park
30078 Hsin-Chu / TW
02 / WEN, Sung-Han
No.1, Dusing 1st Rd.,
Hsinchu Science Park
30078 Hsinchu City / TW
03 / CHEN, Kuan-Ta
No.1, Dusing 1st Rd.,
Hsinchu Science Park
30078 Hsinchu City / TW
 [2021/41]
Former [2020/05]01 / HSIAO, Chuan-Hung
No.1, Dusing Rd. 1st, Science-Based Industrial
Park
30078 Hsin-Chu / TW
02 / WEN, Sung-Han
No.1, Dusing Rd. 1st, Science-Based Industrial
Park
30078 Hsin-Chu / TW
03 / CHEN, Kuan-Ta
No.1, Dusing Rd. 1st, Science-Based Industrial
Park
30078 Hsin-Chu / TW
Representative(s)Haseltine Lake Kempner LLP
Cheapside House
138 Cheapside
London EC2V 6BJ / GB
[2021/41]
Former [2020/05]Haseltine Lake Kempner LLP
Lincoln House, 5th Floor
300 High Holborn
London WC1V 7JH / GB
Application number, filing date19187594.722.07.2019
[2020/05]
Priority number, dateUS201862701885P23.07.2018         Original published format: US 201862701885 P
US20191651505618.07.2019         Original published format: US201916515056
[2020/05]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP3599722
Date:29.01.2020
Language:EN
[2020/05]
Type: B1 Patent specification 
No.:EP3599722
Date:13.10.2021
Language:EN
[2021/41]
Search report(s)(Supplementary) European search report - dispatched on:EP17.12.2019
ClassificationIPC:H03M1/06, H03M1/68, H03M7/36
[2020/05]
CPC:
H03M1/0665 (EP,US); H03M1/662 (CN); H03M1/687 (US);
H03M1/06 (CN); H03M1/0668 (EP,US); H03M1/067 (EP,US);
H03M1/68 (EP,US); H03M7/3026 (EP,US) (-)
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2020/36]
Former [2020/05]AL,  AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  HR,  HU,  IE,  IS,  IT,  LI,  LT,  LU,  LV,  MC,  MK,  MT,  NL,  NO,  PL,  PT,  RO,  RS,  SE,  SI,  SK,  SM,  TR 
TitleGerman:DIGITAL/ANALOG-WANDLER MIT HOHER LINEARITÄT UND ISI-UNTERDRÜCKUNGSVERFAHREN[2020/05]
English:HIGH LINEARITY DIGITAL-TO-ANALOG CONVERTER WITH ISI-SUPPRESSING METHOD[2020/05]
French:CONVERTISSEUR NUMÉRIQUE-ANALOGIQUE À HAUTE LINÉARITÉ COMPORTANT UN PROCÉDÉ DE SUPPRESSION D'ISI[2020/05]
Examination procedure16.06.2020Amendment by applicant (claims and/or description)
26.07.2020Examination requested  [2020/36]
26.07.2020Date on which the examining division has become responsible
03.05.2021Communication of intention to grant the patent
03.09.2021Fee for grant paid
03.09.2021Fee for publishing/printing paid
03.09.2021Receipt of the translation of the claim(s)
Opposition(s)14.07.2022No opposition filed within time limit [2022/38]
Fees paidRenewal fee
30.07.2021Renewal fee patent year 03
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Lapses during opposition  TooltipHU22.07.2019
AL13.10.2021
AT13.10.2021
CY13.10.2021
CZ13.10.2021
DK13.10.2021
EE13.10.2021
ES13.10.2021
FI13.10.2021
HR13.10.2021
IT13.10.2021
LT13.10.2021
LV13.10.2021
MC13.10.2021
MK13.10.2021
NL13.10.2021
PL13.10.2021
RO13.10.2021
RS13.10.2021
SE13.10.2021
SI13.10.2021
SK13.10.2021
SM13.10.2021
TR13.10.2021
BG13.01.2022
NO13.01.2022
GR14.01.2022
IS13.02.2022
PT14.02.2022
[2024/29]
Former [2024/23]HU22.07.2019
AL13.10.2021
AT13.10.2021
CY13.10.2021
CZ13.10.2021
DK13.10.2021
EE13.10.2021
ES13.10.2021
FI13.10.2021
HR13.10.2021
IT13.10.2021
LT13.10.2021
LV13.10.2021
MC13.10.2021
MK13.10.2021
NL13.10.2021
PL13.10.2021
RO13.10.2021
RS13.10.2021
SE13.10.2021
SI13.10.2021
SK13.10.2021
SM13.10.2021
BG13.01.2022
NO13.01.2022
GR14.01.2022
IS13.02.2022
PT14.02.2022
Former [2024/20]HU22.07.2019
AL13.10.2021
AT13.10.2021
CY13.10.2021
CZ13.10.2021
DK13.10.2021
EE13.10.2021
ES13.10.2021
FI13.10.2021
HR13.10.2021
IT13.10.2021
LT13.10.2021
LV13.10.2021
MC13.10.2021
NL13.10.2021
PL13.10.2021
RO13.10.2021
RS13.10.2021
SE13.10.2021
SI13.10.2021
SK13.10.2021
SM13.10.2021
BG13.01.2022
NO13.01.2022
GR14.01.2022
IS13.02.2022
PT14.02.2022
Former [2024/18]HU22.07.2019
AL13.10.2021
AT13.10.2021
CZ13.10.2021
DK13.10.2021
EE13.10.2021
ES13.10.2021
FI13.10.2021
HR13.10.2021
IT13.10.2021
LT13.10.2021
LV13.10.2021
MC13.10.2021
NL13.10.2021
PL13.10.2021
RO13.10.2021
RS13.10.2021
SE13.10.2021
SI13.10.2021
SK13.10.2021
SM13.10.2021
BG13.01.2022
NO13.01.2022
GR14.01.2022
IS13.02.2022
PT14.02.2022
Former [2023/27]AL13.10.2021
AT13.10.2021
CZ13.10.2021
DK13.10.2021
EE13.10.2021
ES13.10.2021
FI13.10.2021
HR13.10.2021
IT13.10.2021
LT13.10.2021
LV13.10.2021
MC13.10.2021
NL13.10.2021
PL13.10.2021
RO13.10.2021
RS13.10.2021
SE13.10.2021
SI13.10.2021
SK13.10.2021
SM13.10.2021
BG13.01.2022
NO13.01.2022
GR14.01.2022
IS13.02.2022
PT14.02.2022
Former [2023/11]AL13.10.2021
AT13.10.2021
CZ13.10.2021
DK13.10.2021
EE13.10.2021
ES13.10.2021
FI13.10.2021
HR13.10.2021
LT13.10.2021
LV13.10.2021
MC13.10.2021
NL13.10.2021
PL13.10.2021
RO13.10.2021
RS13.10.2021
SE13.10.2021
SI13.10.2021
SK13.10.2021
SM13.10.2021
BG13.01.2022
NO13.01.2022
GR14.01.2022
IS13.02.2022
PT14.02.2022
Former [2023/01]AL13.10.2021
AT13.10.2021
CZ13.10.2021
DK13.10.2021
EE13.10.2021
ES13.10.2021
FI13.10.2021
HR13.10.2021
LT13.10.2021
LV13.10.2021
NL13.10.2021
PL13.10.2021
RO13.10.2021
RS13.10.2021
SE13.10.2021
SI13.10.2021
SK13.10.2021
SM13.10.2021
BG13.01.2022
NO13.01.2022
GR14.01.2022
IS13.02.2022
PT14.02.2022
Former [2022/49]AL13.10.2021
AT13.10.2021
CZ13.10.2021
DK13.10.2021
EE13.10.2021
ES13.10.2021
FI13.10.2021
HR13.10.2021
LT13.10.2021
LV13.10.2021
NL13.10.2021
PL13.10.2021
RO13.10.2021
RS13.10.2021
SE13.10.2021
SK13.10.2021
SM13.10.2021
BG13.01.2022
NO13.01.2022
GR14.01.2022
IS13.02.2022
PT14.02.2022
Former [2022/35]AT13.10.2021
CZ13.10.2021
DK13.10.2021
EE13.10.2021
ES13.10.2021
FI13.10.2021
HR13.10.2021
LT13.10.2021
LV13.10.2021
NL13.10.2021
PL13.10.2021
RO13.10.2021
RS13.10.2021
SE13.10.2021
SK13.10.2021
SM13.10.2021
BG13.01.2022
NO13.01.2022
GR14.01.2022
IS13.02.2022
PT14.02.2022
Former [2022/34]AT13.10.2021
EE13.10.2021
ES13.10.2021
FI13.10.2021
HR13.10.2021
LT13.10.2021
LV13.10.2021
NL13.10.2021
PL13.10.2021
RO13.10.2021
RS13.10.2021
SE13.10.2021
SM13.10.2021
BG13.01.2022
NO13.01.2022
GR14.01.2022
IS13.02.2022
PT14.02.2022
Former [2022/33]AT13.10.2021
ES13.10.2021
FI13.10.2021
HR13.10.2021
LT13.10.2021
LV13.10.2021
NL13.10.2021
PL13.10.2021
RS13.10.2021
SE13.10.2021
SM13.10.2021
BG13.01.2022
NO13.01.2022
GR14.01.2022
IS13.02.2022
PT14.02.2022
Former [2022/25]AT13.10.2021
ES13.10.2021
FI13.10.2021
HR13.10.2021
LT13.10.2021
LV13.10.2021
NL13.10.2021
PL13.10.2021
RS13.10.2021
SE13.10.2021
BG13.01.2022
NO13.01.2022
GR14.01.2022
IS13.02.2022
PT14.02.2022
Former [2022/24]AT13.10.2021
ES13.10.2021
FI13.10.2021
HR13.10.2021
LT13.10.2021
LV13.10.2021
NL13.10.2021
PL13.10.2021
RS13.10.2021
SE13.10.2021
BG13.01.2022
GR14.01.2022
IS13.02.2022
PT14.02.2022
Former [2022/23]AT13.10.2021
ES13.10.2021
FI13.10.2021
HR13.10.2021
LT13.10.2021
LV13.10.2021
PL13.10.2021
RS13.10.2021
BG13.01.2022
PT14.02.2022
Former [2022/22]AT13.10.2021
FI13.10.2021
LT13.10.2021
RS13.10.2021
BG13.01.2022
Former [2022/21]AT13.10.2021
RS13.10.2021
BG13.01.2022
Former [2022/19]BG13.01.2022
Documents cited:Search[XI]EP3288186  (MEDIATEK INC [TW]) [X] 1,9 * paragraphs [0065] , [0067]; figure 16 * [I] 2-5,10-13;
 [XI]  - R Adams ET AL, "A 113-dB SNR oversampling DAC with segmented noise-shaped scrambling", IEEE Journal of Solid-State Circuits, doi:10.1109/4.735526, (19981212), pages 1871 - 1878, URL: http://ieeexplore.ieee.org/ielx4/4/15831/00735526.pdf?tp=&arnumber=735526&isnumber=15831, (20160628), XP055284296 [X] 1,9 * page 1874, column r, paragraph 2 - page 1875, column l, paragraph 1; figure 10 * [I] 2-5,10-13

DOI:   http://dx.doi.org/10.1109/4.735526
 [A]  - VAN TUIJL E ET AL, "20.5 - A 128f/sub s/ Multi-Bit /spl Sigma//spl Delta/ CMOS Audio DAC with Real-Time DEM and 115dB SFDR", SOLID-STATE CIRCUITS CONFERENCE, 2004. DIGEST OF TECHNICAL PAPERS. ISSCC. 2004 IEEE INTERNATIONAL, IEEE, PISCATAWAY, NJ, USA, (20040215), doi:10.1109/ISSCC.2004.1332747, ISBN 978-0-7803-8267-1, pages 368 - 375, XP010722306 [A] 5-8,13-15 * page 1, column l, paragraph 1 - paragraph 2; figures 20.5.1,20.5.2 *

DOI:   http://dx.doi.org/10.1109/ISSCC.2004.1332747
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