EP3686814 - HYBRID CPU AND ANALOG IN-MEMORY ARTIFICIAL INTELLIGENCE PROCESSOR [Right-click to bookmark this link] | Status | Examination is in progress Status updated on 27.01.2023 Database last updated on 16.07.2024 | |
Former | Request for examination was made Status updated on 29.01.2021 | ||
Former | The application has been published Status updated on 26.06.2020 | Most recent event Tooltip | 25.02.2024 | New entry: Date of oral proceedings | Applicant(s) | For all designated states INTEL Corporation 2200 Mission College Blvd. Santa Clara, CA 95054 / US | [2020/31] | Inventor(s) | 01 /
YOUNG, Ian Intel Corporation 3181 NW 114th Terrace Portland, OR 97229 / US | 02 /
KRISHNAMURTHY, Ram Intel Corporation 13042 NW Bertani Street Portland, OR 97229 / US | 03 /
NIKONOV, Dmitri Intel Corporation 16569 SW Whitetail Ln. Beaverton, OR 97007 / US | 04 /
MANIPATRUNI, Sasikanth Intel Corporation 16335 NW Rossetta Portland, OR 97229 / US | 05 /
MATHURIYA, Amrita Intel Corporation 16335 NW Rossetta Street Portland, OR 97229 / US | [2020/31] | Representative(s) | Goddar, Heinz J. Boehmert & Boehmert Anwaltspartnerschaft mbB Pettenkoferstrasse 22 80336 München / DE | [2020/31] | Application number, filing date | 19199361.7 | 24.09.2019 | [2020/31] | Priority number, date | US201916258522 | 25.01.2019 Original published format: US201916258522 | [2020/31] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP3686814 | Date: | 29.07.2020 | Language: | EN | [2020/31] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 22.04.2020 | Classification | IPC: | G06N3/063, G06N3/04 | [2020/31] | CPC: |
G06N3/065 (EP,US);
G06F17/16 (US);
G06N3/04 (US);
G06N3/045 (EP);
G06N3/048 (EP)
| Designated contracting states | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR [2021/09] |
Former [2020/31] | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR | Extension states | BA | Not yet paid | ME | Not yet paid | Validation states | KH | Not yet paid | MA | Not yet paid | MD | Not yet paid | TN | Not yet paid | Title | German: | HYBRIDE CPU UND ANALOGER SPEICHERINTERNER PROZESSOR MIT KÜNSTLICHER INTELLIGENZ | [2020/31] | English: | HYBRID CPU AND ANALOG IN-MEMORY ARTIFICIAL INTELLIGENCE PROCESSOR | [2020/31] | French: | CPU HYBRIDE ET PROCESSEUR D'INTELLIGENCE ARTIFICIELLE EN MÉMOIRE ANALOGIQUE | [2020/31] | Examination procedure | 22.01.2021 | Amendment by applicant (claims and/or description) | 22.01.2021 | Examination requested [2021/09] | 22.01.2021 | Date on which the examining division has become responsible | 27.01.2023 | Despatch of a communication from the examining division (Time limit: M04) | 23.05.2023 | Reply to a communication from the examining division | 08.10.2024 | Date of oral proceedings | Fees paid | Renewal fee | 13.09.2021 | Renewal fee patent year 03 | 26.08.2022 | Renewal fee patent year 04 | 29.08.2023 | Renewal fee patent year 05 |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]US2016284400 (YAKOPCIC CHRIS [US], et al) [A] 1-15 * abstract * * paragraph [0002] * * paragraph [0007] - paragraph [0009] ** paragraph [0021] - paragraph [0067] *; | [XI]US10176425 (YAKOPCIC CHRIS [US], et al) [X] 1-11,13-15 * abstract * * column 1, line 15 - column 3, line 12 * * column 4, line 34 - column 40, line 21 * [I] 12; | [A] - LI Y ET AL, "Capacitor-based Cross-point Array for Analog Neural Network with Record Symmetry and Linearity", 2018 IEEE SYMPOSIUM ON VLSI TECHNOLOGY, IEEE, (20180618), doi:10.1109/VLSIT.2018.8510648, pages 25 - 26, XP033429820 [A] 1-15 * abstract * * page 25, column l, line 1 - column r, line l * DOI: http://dx.doi.org/10.1109/VLSIT.2018.8510648 |