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Extract from the Register of European Patents

EP About this file: EP3811246

EP3811246 - EFFICIENT INTEGRATED CIRCUIT SIMULATION AND TESTING [Right-click to bookmark this link]
StatusRequest for examination was made
Status updated on  26.03.2021
Database last updated on 14.11.2024
FormerThe international publication has been made
Status updated on  27.12.2019
Most recent event   Tooltip17.06.2024New entry: Renewal fee paid 
Applicant(s)For all designated states
Proteantecs Ltd.
2 Pal-Yam Ave.
3309502 Haifa / IL
[2021/17]
Inventor(s)01 / LANDMAN, Evelyn
34 Ester Rabin St.
3491795 Haifa / IL
02 / TALKER, Yair
17 Hagefen St.
3050000 Binyamina / IL
03 / FAYNEH, Eyal
1 Hamorad St.
5322001 Givatayim / IL
04 / DAVID, Yahel
Kibbutz
Gazit 1934000 / IL
05 / COHEN, Shai
23 Hatishbi St.
3452718 Haifa / IL
06 / WEINTROB, Inbar
22 Halivne St.
3780800 Givat-Ada / IL
07 / DAVID, Yahel
Kibbutz
Gazit 1934000 / IL
 [2021/17]
Representative(s)Boult Wade Tennant LLP
Salisbury Square House
8 Salisbury Square
London EC4Y 8AP / GB
[2021/17]
Application number, filing date19823036.919.06.2019
[2021/17]
WO2019IL50686
Priority number, dateUS201862686744P19.06.2018         Original published format: US 201862686744 P
[2021/17]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report
No.:WO2019244154
Date:26.12.2019
Language:EN
[2019/52]
Type: A1 Application with search report 
No.:EP3811246
Date:28.04.2021
Language:EN
The application published by WIPO in one of the EPO official languages on 26.12.2019 takes the place of the publication of the European patent application.
[2021/17]
Search report(s)International search report - published on:IL26.12.2019
(Supplementary) European search report - dispatched on:EP18.02.2022
ClassificationIPC:G06F30/3315, G06F30/3312, G06F30/398, // G06F111/08, G06F119/06, G06F119/22, G06F119/02, G06F119/12, G06F119/04
[2022/12]
CPC:
G06F30/3315 (EP); G06F30/3312 (EP,US); G06F30/398 (EP);
G06F2111/08 (EP,US); G06F2119/02 (EP); G06F2119/04 (EP);
G06F2119/06 (EP,US); G06F2119/12 (EP); G06F2119/22 (EP,US) (-)
Former IPC [2021/17]G06F17/50
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2021/17]
TitleGerman:EFFIZIENTE SIMULATION UND PRÜFUNG EINER INTEGRIERTEN SCHALTUNG[2021/17]
English:EFFICIENT INTEGRATED CIRCUIT SIMULATION AND TESTING[2021/17]
French:SIMULATION ET TEST DE CIRCUIT INTÉGRÉ EFFICACES[2021/17]
Entry into regional phase14.01.2021National basic fee paid 
14.01.2021Search fee paid 
14.01.2021Designation fee(s) paid 
14.01.2021Examination fee paid 
Examination procedure14.01.2021Examination requested  [2021/17]
11.10.2022Despatch of communication that the application is deemed to be withdrawn, reason: reply to the Extended European Search Report/Written Opinion of the International Searching Authority/International Preliminary Examination Report/Supplementary international search report not received in time
19.12.2022Amendment by applicant (claims and/or description)
Request for further processing for:The application is deemed to be withdrawn due to failure to reply to the Extended European Search Report/Written Opinion of the International Searching Authority/International Preliminary Examination Report/Supplementary international search report/Supplementary European search report
19.12.2022Request for further processing filed
19.12.2022Full payment received (date of receipt of payment)
Request granted
03.01.2023Decision despatched
Fees paidRenewal fee
15.06.2021Renewal fee patent year 03
15.06.2022Renewal fee patent year 04
27.06.2023Renewal fee patent year 05
16.06.2024Renewal fee patent year 06
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Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[I]EP2006784  (IMEC INTER UNI MICRO ELECTR [BE]) [I] 1-15 * abstract * * paragraph [0007] * * paragraph [0014] - paragraph [0019] * * paragraph [0024] * * paragraph [0041] - paragraph [0059] * * paragraph [0062] * * paragraph [0099] - paragraph [0137] *;
 [Y]  - VIVEK S NANDAKUMAR ET AL, "Statistical static timing analysis flow for transistor level macros in a microprocessor", QUALITY ELECTRONIC DESIGN (ISQED), 2010 11TH INTERNATIONAL SYMPOSIUM ON, IEEE, PISCATAWAY, NJ, USA, (20100322), doi:10.1109/ISQED.2010.5450412, ISBN 978-1-4244-6454-8, pages 163 - 170, XP032393108 [Y] 1-15 * abstract * * page 163, column 2 - page 168 *

DOI:   http://dx.doi.org/10.1109/ISQED.2010.5450412
 [Y]  - JING LI ET AL, "Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications", IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, IEEE, USA, (20090101), vol. 28, no. 1, doi:10.1109/TCAD.2008.2009149, ISSN 0278-0070, pages 46 - 59, XP011240734 [Y] 1-15 * abstract * * page 50 - page 52 *

DOI:   http://dx.doi.org/10.1109/TCAD.2008.2009149
 [A]  - XIE QING ET AL, "Variation-aware joint optimization of the supply voltage and sleep transistor size for the 7nm FinFET technology", 2014 IEEE 32ND INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), IEEE, (20141019), doi:10.1109/ICCD.2014.6974709, pages 380 - 385, XP032695620 [A] 1-15 * abstract * * page 381 - page 385 *

DOI:   http://dx.doi.org/10.1109/ICCD.2014.6974709
 [A]  - REBAUD B ET AL, "Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization", MICROELECTRONICS JOURNAL, MACKINTOSH PUBLICATIONS LTD. LUTON, GB, vol. 42, no. 5, doi:10.1016/J.MEJO.2011.02.005, ISSN 0026-2692, (20110208), pages 718 - 732, (20110215), XP028198779 [A] 1-15 * the whole document *

DOI:   http://dx.doi.org/10.1016/j.mejo.2011.02.005
 [A]  - DIERICKX B ET AL, "Propagating variability from technology to system level", PHYSICS OF SEMICONDUCTOR DEVICES, 2007. IWPSD 2007. INTERNATIONAL WORKSHOP ON, IEEE, PISCATAWAY, NJ, USA, (20071216), ISBN 978-1-4244-1727-8, pages 74 - 79, XP031238544 [A] 1-15 * abstract * * page 4 *
International search[Y]US2009306953  (LIU JINFENG [US], et al) [Y] 7, 9, 12-14* 1) 55-56 *;
 [XY]US2011093830  (CHEN QIANG [US], et al) [X] 1-6, 8, 10, 11, 15-18 * 13-14, 30-33, 53, 56, 62-69 * [Y] 7, 9, 12-14
by applicantEP2006784
    - VIVEK S NANDAKUMAR et al., "Statistical static timing analysis flow for transistor level macros in a microprocessor", QUALITY ELECTRONIC DESIGN (ISQED), 2010 11TH INTERNATIONAL SYMPOS ON, IEEE, PISCATAWAY, NJ, USA, (20100322), doi:10.1109/ISQED.2010.5450412, pages 163 - 170, XP032393108

DOI:   http://dx.doi.org/10.1109/ISQED.2010.5450412
    - JING LI et al., "Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications", IEEE
    - SYSTEMS, IEEE, USA, (20090101), vol. 28, pages 46 - 59
    - XIE QING et al., "Variation-aware joint optimization of the supply voltage and sleep transistor size for the 7nm FinFET technology", 2014 IEEE 32ND INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), IEEE, (20141019), doi:10.1109/ICCD.2014.6974709, pages 380 - 385, XP032695620

DOI:   http://dx.doi.org/10.1109/ICCD.2014.6974709
    - REBAUD B et al., "Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization", MICROELECTRONICS JOURNAL, MACKINTOSH PUBLICATIONS LTD. LUTON, GB, (20110208), vol. 42, no. 5, doi:10.1016/j.mejo.2011.02.005, pages 718 - 732, XP028198779

DOI:   http://dx.doi.org/10.1016/j.mejo.2011.02.005
    - DIERICKX B et al., "Propagating variability from technology to system level", PHYSICS OF SEMICONDUCTOR DEVICES, 2007. IWPSD 2007. INTERNATIONAL WORKSHOP ON, IEEE, PISCATAWAY, NJ, USA, (20071216), pages 74 - 79, XP031238544
 US20060626147
 WO2018IL51234
 WO2019IL50039
 WO2019IL50433
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