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EP3772165
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EP About this file: EP3772165
| EP3772165 - CIRCUIT AND METHOD FOR REDUCING NETWORK SIDE HARMONICS IN THE INPUT FLOW OF A DIODE RECTIFIER [Right-click to bookmark this link] | Status | Examination is in progress Status updated on 27.01.2023 Database last updated on 05.07.2024 | |
| Former | Request for examination was made Status updated on 30.07.2021 | ||
| Former | The application has been published Status updated on 01.01.2021 | Most recent event Tooltip | 27.03.2024 | New entry: Renewal fee paid | Applicant(s) | For all designated states ebm-papst Mulfingen GmbH & Co. KG Bachmühle 2 74673 Mulfingen / DE | [2021/05] | Inventor(s) | 01 /
SCHROTH, Sebastian Johann-Andreas-Stutz-Straße 4 74635 Kupferzell / DE | 02 /
SCHNEIDER, Alex Klebweg 8 74653 Künzelsau / DE | [2021/05] | Representative(s) | Staeger & Sperling Partnerschaftsgesellschaft mbB Sonnenstraße 19 80331 München / DE | [2021/05] | Application number, filing date | 20165529.7 | 25.03.2020 | [2021/05] | Priority number, date | DE201910120682 | 31.07.2019 Original published format: DE102019120682 | [2021/05] | Filing language | DE | Procedural language | DE | Publication | Type: | A1 Application with search report | No.: | EP3772165 | Date: | 03.02.2021 | Language: | DE | [2021/05] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 10.12.2020 | Classification | IPC: | H02M1/12 | [2021/05] | CPC: |
H02M1/4208 (EP);
H02M1/12 (EP);
Y02B70/10 (EP)
| Designated contracting states | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR [2021/35] |
| Former [2021/05] | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR | Extension states | BA | Not yet paid | ME | Not yet paid | Validation states | KH | Not yet paid | MA | Not yet paid | MD | Not yet paid | TN | Not yet paid | Title | German: | SCHALTUNG UND VERFAHREN ZUR REDUKTION NETZSEITIGER OBERWELLEN IM EINGANGSSTROM EINES DIODENGLEICHRICHTERS | [2021/05] | English: | CIRCUIT AND METHOD FOR REDUCING NETWORK SIDE HARMONICS IN THE INPUT FLOW OF A DIODE RECTIFIER | [2021/05] | French: | CIRCUIT ET PROCÉDÉ DE RÉDUCTION DES HARMONIQUES CÔTÉ RÉSEAU DANS LE COURANT D'ENTRÉE D'UN REDRESSEUR À DIODES | [2021/05] | Examination procedure | 27.07.2021 | Amendment by applicant (claims and/or description) | 27.07.2021 | Examination requested [2021/35] | 27.07.2021 | Date on which the examining division has become responsible | 31.01.2023 | Despatch of a communication from the examining division (Time limit: M04) | 01.06.2023 | Reply to a communication from the examining division | Fees paid | Renewal fee | 28.03.2022 | Renewal fee patent year 03 | 27.03.2023 | Renewal fee patent year 04 | 26.03.2024 | Renewal fee patent year 05 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [Y]US5499178 (MOHAN NED [US]) [Y] 11 * figure 5 *; | [X]US6049473 (JANG YUNGTAEK [US], et al) [X] 1,2,4-7 * column 1, line 55 - column 3, line 3 *; | [X]US6295216 (FARIA DES [CA], et al) [X] 1,2,4,5,7,9-11 * column 4 - column 7; figures 1-4 *; | [XY]US2012113691 (VIDET ARNAUD [FR], et al) [X] 1,2,4,5,7-11 * paragraph [0005] - paragraph [0074] * [Y] 3; | [Y]US2013314953 (CUZNER ROBERT M [US], et al) [Y] 10,11 * paragraph [0046] - paragraph [0053]; figure 9 *; | [XY]EP2793386 (PANASONIC CORP [JP]) [X] 1,2,4,5,7-9 * paragraph [0003] - paragraph [0054]; figure 1 * [Y] 3,10,11; | [Y]WO2018158453 (ABB SCHWEIZ AG [CH]) [Y] 3* figures 1-3 * | by applicant | DE102008055875 | DE102011016931 |