Extract from the Register of European Patents

EP About this file: EP3843273

EP3843273 - RANDOMLY SAMPLING REFERENCE ADC FOR CALIBRATION [Right-click to bookmark this link]
StatusThe patent has been granted
Status updated on  31.10.2025
Database last updated on 11.04.2026
FormerGrant of patent is intended
Status updated on  11.07.2025
FormerExamination is in progress
Status updated on  21.07.2023
FormerRequest for examination was made
Status updated on  31.12.2021
FormerThe application has been published
Status updated on  28.05.2021
Most recent event   Tooltip31.10.2025(Expected) grantpublished on 03.12.2025  [2025/49]
Applicant(s)For all designated states
Analog Devices, Inc.
One Analog Way
Wilmington, MA 01887 / US
[2021/26]
Inventor(s)01 / SPEIR, Carroll C.
7037 Hidden Lane Ext
Pleasant Garden, NC 27313 / US
02 / OTTE, Eric
27 Bay State Road, Apt. 3F
Boston, MA 02215 / US
03 / RAKULJIC, Nevena
6625 Radcliffe Drive
San Diego, CA 92122 / US
04 / BRAY, Jeffrey Paul
13272 Courtland Terrace
San Diego, CA 92130 / US
 [2021/26]
Representative(s)Wallin, Nicholas James
Withers & Rogers LLP
2 London Bridge
London SE1 9RA / GB
[2025/49]
Former [2021/26]Wallin, Nicholas James
Withers & Rogers LLP
4 More London Riverside
London SE1 2AU / GB
Application number, filing date21157253.215.12.2015
[2021/26]
Priority number, dateUS201462093391P17.12.2014         Original published format: US 201462093391 P
US20151495588801.12.2015         Original published format: US201514955888
US20151495590501.12.2015         Original published format: US201514955905
US20151495591601.12.2015         Original published format: US201514955916
[2021/26]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP3843273
Date:30.06.2021
Language:EN
[2021/26]
Type: B1 Patent specification 
No.:EP3843273
Date:03.12.2025
Language:EN
[2025/49]
Search report(s)(Supplementary) European search report - dispatched on:EP31.05.2021
ClassificationIPC:H03M1/06, H03M1/10, H03M1/08, // H03M1/12, H03M1/16
[2021/26]
CPC:
H03M1/1028 (EP); H03M1/0673 (EP); H03M1/1004 (EP);
H03M1/1215 (EP); H03M1/164 (EP)
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2022/05]
Former [2021/26]AL,  AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  HR,  HU,  IE,  IS,  IT,  LI,  LT,  LU,  LV,  MC,  MK,  MT,  NL,  NO,  PL,  PT,  RO,  RS,  SE,  SI,  SK,  SM,  TR 
TitleGerman:ZUFÄLLIGE ABTASTUNG DES REFERENZ-ADCS ZUR KALIBRIERUNG[2025/32]
English:RANDOMLY SAMPLING REFERENCE ADC FOR CALIBRATION[2021/26]
French:ÉCHANTILLONNAGE ALÉATOIRE DU CAN DE RÉFÉRENCE POUR L'ÉTALONNAGE[2025/32]
Former [2021/26]ZUFÄLLIG ABGETASTETES REFERENZ-ANTIKÖRPER-ARZNEIMITTEL-KONJUGAT (ADC) ZUR KALIBRIERUNG
Former [2021/26]CAN DE RÉFÉRENCE D'ÉCHANTILLONNAGE ALÉATOIRE POUR ÉTALONNAGE
Examination procedure23.12.2021Amendment by applicant (claims and/or description)
23.12.2021Examination requested  [2022/05]
23.12.2021Date on which the examining division has become responsible
24.07.2023Despatch of a communication from the examining division (Time limit: M04)
08.11.2023Reply to a communication from the examining division
11.07.2025Communication of intention to grant the patent
24.10.2025Fee for grant paid
24.10.2025Fee for publishing/printing paid
24.10.2025Receipt of the translation of the claim(s)
Parent application(s)   TooltipEP15200032.9  / EP3043478
EP20212305.5  / EP3836403
Fees paidRenewal fee
15.02.2021Renewal fee patent year 03
15.02.2021Renewal fee patent year 04
15.02.2021Renewal fee patent year 05
15.02.2021Renewal fee patent year 06
16.12.2021Renewal fee patent year 07
20.12.2022Renewal fee patent year 08
19.12.2023Renewal fee patent year 09
19.12.2024Renewal fee patent year 10
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Documents cited:Search[XI] US2014152478  (LEWIS DONALD E et al.)
 [X] US6900750  (NAIRN DAVID G et al.)
 [A] US7227479  (CHEN HSIN-HUNG et al.)
 [A]   K.C DYER ET AL: "An analog background calibration technique for time-interleaved analog-to-digital converters", IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1 December 1998 (1998-12-01), pages 1912 - 1919, XP055716072, Retrieved from the Internet DOI: 10.1109/4.735531

DOI:   http://dx.doi.org/10.1109/4.735531
 [A]   MAYES M K ET AL: "A 200 MW, 1 MSAMPLE/S, 16-B PIPELINE A/D CONVERTER WITH ON-CHIP 32-B MICOCONTROLLER", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE, USA, vol. 31, no. 12, 1 December 1996 (1996-12-01), pages 1862 - 1872, XP000691803, ISSN: 0018-9200, DOI: 10.1109/4.545806

DOI:   http://dx.doi.org/10.1109/4.545806
 [A]   ANDERSON M ET AL: "Verification of a blind mismatch error equalization method for randomly interleaved ADCs using a 2.5V/12b/30MSs PSAADC", EUROPEAN SOLID-STATE CIRCUITS, 2003. ESSCIRC '03. CONFERENCE ON 16-18 SEPT. 2003, IEEE, PISCATAWAY, NJ, USA, 16 September 2003 (2003-09-16), pages 473 - 476, XP032156433, ISBN: 978-0-7803-7995-4, DOI: 10.1109/ESSCIRC.2003.1257175

DOI:   http://dx.doi.org/10.1109/ESSCIRC.2003.1257175
ExaminationUS2013321053
   CROUGHWELL ROSAMARIA: "A 16-b 10Msample/s Split-Interleaved Analog to Digital Converter", ELECTRONIC THESES AND DISSERTATIONS, 24 August 2007 (2007-08-24), pages 1 - 115, XP093064287, Retrieved from the Internet [retrieved on 20230714]
   FRANCESCO CENTURELLI ET AL: "Efficient Digital Background Calibration of Time-Interleaved Pipeline Analog-to-Digital Converters", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, IEEE, US, vol. 59, no. 7, 1 July 2012 (2012-07-01), pages 1373 - 1383, XP011448559, ISSN: 1549-8328, DOI: 10.1109/TCSI.2011.2177003

DOI:   http://dx.doi.org/10.1109/TCSI.2011.2177003
   BAZRAFSHAN AMIR ET AL: "A low-complexity digital background calibration of sample-time error in time-interleaved A/D converters", ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, SPRINGER NEW YORK LLC, US, vol. 76, no. 2, 23 May 2013 (2013-05-23), pages 245 - 249, XP035311758, ISSN: 0925-1030, [retrieved on 20130523], DOI: 10.1007/S10470-013-0078-Y

DOI:   http://dx.doi.org/10.1007/s10470-013-0078-y
   WENBO LIU ET AL: "Time-Interleaved Analog-to-Digital Conversion With Online Adaptive Equalization", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, IEEE, US, vol. 59, no. 7, 1 July 2012 (2012-07-01), pages 1384 - 1395, XP011448564, ISSN: 1549-8328, DOI: 10.1109/TCSI.2011.2177005

DOI:   http://dx.doi.org/10.1109/TCSI.2011.2177005
   TIM REGAN ET AL: "Easy-to-Use Spread Spectrum Clock Generator Reduces EMI and More", LINEAR TECHNOLOGY MAGAZINE, 1 February 2004 (2004-02-01), pages 6 - 12, XP055274126, Retrieved from the Internet [retrieved on 20160520]
by applicantUS201462093391
 EP15200032
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