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Extract from the Register of European Patents

EP About this file: EP3872621

EP3872621 - LOOK AHEAD NORMALISER [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  24.02.2023
Database last updated on 16.11.2024
FormerThe patent has been granted
Status updated on  18.03.2022
FormerGrant of patent is intended
Status updated on  21.11.2021
FormerRequest for examination was made
Status updated on  30.07.2021
Most recent event   Tooltip15.11.2024Change - lapse in a contracting state
Updated state(s): BG		published on 18.12.2024 [2024/51]
Applicant(s)For all designated states
Imagination Technologies Limited
Imagination House
Home Park Estate
Kings Langley
Hertfordshire WD4 8LZ / GB
[2021/35]
Inventor(s)01 / VAN BENTHEM, Casper
Imagination House
Home Park Estate
Kings Langley, Hertfordshire WD4 8LZ / GB
 [2021/35]
Representative(s)CMS Cameron McKenna Nabarro Olswang LLP
Cannon Place
78 Cannon Street
London EC4N 6AF / GB
[2021/35]
Application number, filing date21158917.124.02.2021
[2021/35]
Priority number, dateGB2020000288328.02.2020         Original published format: GB 202002883
[2021/35]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP3872621
Date:01.09.2021
Language:EN
[2021/35]
Type: B1 Patent specification 
No.:EP3872621
Date:20.04.2022
Language:EN
[2022/16]
Type: B8 Corrected title page of specification 
No.:EP3872621
Date:01.06.2022
[2022/22]
Search report(s)(Supplementary) European search report - dispatched on:EP08.07.2021
ClassificationIPC:G06F7/499
[2021/35]
CPC:
G06F7/49936 (EP,US); G06F9/30025 (CN); G06F5/01 (GB,US);
G06F5/012 (GB); G06F7/499 (GB)
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2022/19]
Former [2021/35]AL,  AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  HR,  HU,  IE,  IS,  IT,  LI,  LT,  LU,  LV,  MC,  MK,  MT,  NL,  NO,  PL,  PT,  RO,  RS,  SE,  SI,  SK,  SM,  TR 
TitleGerman:LOOK-AHEAD-NORMALISIERER[2021/35]
English:LOOK AHEAD NORMALISER[2021/35]
French:NORMALISATEUR D'ANTICIPATION[2021/35]
Examination procedure08.07.2021Examination requested  [2021/35]
08.07.2021Date on which the examining division has become responsible
22.11.2021Communication of intention to grant the patent
11.03.2022Fee for grant paid
11.03.2022Fee for publishing/printing paid
11.03.2022Receipt of the translation of the claim(s)
08.04.2022Request for correction of the decision to grant filed
Opposition(s)23.01.2023No opposition filed within time limit [2023/13]
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipAL20.04.2022
AT20.04.2022
BG20.04.2022
CZ20.04.2022
DK20.04.2022
EE20.04.2022
ES20.04.2022
FI20.04.2022
HR20.04.2022
IT20.04.2022
LT20.04.2022
LV20.04.2022
MC20.04.2022
NL20.04.2022
PL20.04.2022
RO20.04.2022
RS20.04.2022
SE20.04.2022
SK20.04.2022
SM20.04.2022
NO20.07.2022
GR21.07.2022
IS20.08.2022
PT22.08.2022
[2024/51]
Former [2024/11]AL20.04.2022
AT20.04.2022
CZ20.04.2022
DK20.04.2022
EE20.04.2022
ES20.04.2022
FI20.04.2022
HR20.04.2022
IT20.04.2022
LT20.04.2022
LV20.04.2022
MC20.04.2022
NL20.04.2022
PL20.04.2022
RO20.04.2022
RS20.04.2022
SE20.04.2022
SK20.04.2022
SM20.04.2022
BG20.07.2022
NO20.07.2022
GR21.07.2022
IS20.08.2022
PT22.08.2022
Former [2023/44]AL20.04.2022
AT20.04.2022
CZ20.04.2022
DK20.04.2022
EE20.04.2022
ES20.04.2022
FI20.04.2022
HR20.04.2022
LT20.04.2022
LV20.04.2022
MC20.04.2022
NL20.04.2022
PL20.04.2022
RO20.04.2022
RS20.04.2022
SE20.04.2022
SK20.04.2022
SM20.04.2022
BG20.07.2022
NO20.07.2022
GR21.07.2022
IS20.08.2022
PT22.08.2022
Former [2023/17]AL20.04.2022
AT20.04.2022
CZ20.04.2022
DK20.04.2022
EE20.04.2022
ES20.04.2022
FI20.04.2022
HR20.04.2022
LT20.04.2022
LV20.04.2022
NL20.04.2022
PL20.04.2022
RO20.04.2022
RS20.04.2022
SE20.04.2022
SK20.04.2022
SM20.04.2022
BG20.07.2022
NO20.07.2022
GR21.07.2022
IS20.08.2022
PT22.08.2022
Former [2023/09]AT20.04.2022
CZ20.04.2022
DK20.04.2022
EE20.04.2022
ES20.04.2022
FI20.04.2022
HR20.04.2022
LT20.04.2022
LV20.04.2022
NL20.04.2022
PL20.04.2022
RO20.04.2022
RS20.04.2022
SE20.04.2022
SK20.04.2022
SM20.04.2022
BG20.07.2022
NO20.07.2022
GR21.07.2022
IS20.08.2022
PT22.08.2022
Former [2023/07]AT20.04.2022
DK20.04.2022
ES20.04.2022
FI20.04.2022
HR20.04.2022
LT20.04.2022
LV20.04.2022
NL20.04.2022
PL20.04.2022
RS20.04.2022
SE20.04.2022
BG20.07.2022
NO20.07.2022
GR21.07.2022
IS20.08.2022
PT22.08.2022
Former [2022/51]AT20.04.2022
ES20.04.2022
FI20.04.2022
HR20.04.2022
LT20.04.2022
LV20.04.2022
NL20.04.2022
PL20.04.2022
RS20.04.2022
SE20.04.2022
BG20.07.2022
NO20.07.2022
GR21.07.2022
IS20.08.2022
PT22.08.2022
Former [2022/50]AT20.04.2022
ES20.04.2022
FI20.04.2022
HR20.04.2022
LT20.04.2022
LV20.04.2022
NL20.04.2022
PL20.04.2022
RS20.04.2022
SE20.04.2022
BG20.07.2022
NO20.07.2022
GR21.07.2022
PT22.08.2022
Former [2022/49]AT20.04.2022
ES20.04.2022
FI20.04.2022
HR20.04.2022
LT20.04.2022
LV20.04.2022
NL20.04.2022
SE20.04.2022
BG20.07.2022
NO20.07.2022
GR21.07.2022
PT22.08.2022
Former [2022/47]AT20.04.2022
ES20.04.2022
FI20.04.2022
LT20.04.2022
NL20.04.2022
SE20.04.2022
NO20.07.2022
PT22.08.2022
Former [2022/44]NL20.04.2022
Documents cited:Search[A]US5241490  (POON JACK T [US]) [A] 1-14 * column 6, line 21 - line 42; figure 14 *;
 [A]US2017300297  (DRANE THEO ALAN [GB]) [A] 1-14 * paragraphs [0025] - [0043] - [0067] - [0075] *;
 [A]  - Vojin G Oklobdzija, "Transactions Briefs An Algorithmic and Novel Design of a Leading Zero Detector Circuit: Comparison with Logic Synthesis", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, (19940101), URL: https://www.csee.umbc.edu/~phatak/645/supl/lza/vojin-lza-design-tvlsi-94.pdf, XP055743912 [A] 1-14 * section II *
 [A]  - DIMITRAKOPOULOS G ET AL, "Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, (20080701), vol. 16, no. 7, doi:10.1109/TVLSI.2008.2000458, ISSN 1063-8210, pages 837 - 850, XP011227885 [A] 1-14 * page 838, column r, paragraph l - page 839, column l, paragraph 2 *

DOI:   http://dx.doi.org/10.1109/TVLSI.2008.2000458
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.