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Extract from the Register of European Patents

EP About this file: EP3907885

EP3907885 - LOW VOLTAGE CLOCK SWING TOLERANT SEQUENTIAL CIRCUITS FOR DYNAMIC POWER SAVINGS [Right-click to bookmark this link]
Former [2021/45]LOW VOLTAGE CLOCK SWING TOLERANT SEQUENTIAL CIRCUITS FOR DYNAMIC POWER SAVING
[2022/39]
StatusNo opposition filed within time limit
Status updated on  22.12.2023
Database last updated on 25.09.2024
FormerThe patent has been granted
Status updated on  13.01.2023
FormerGrant of patent is intended
Status updated on  28.08.2022
FormerRequest for examination was made
Status updated on  08.10.2021
Most recent event   Tooltip31.05.2024Lapse of the patent in a contracting state
New state(s): IT
published on 03.07.2024  [2024/27]
Applicant(s)For all designated states
Apple Inc.
One Apple Park Way
Cupertino, CA 95014 / US
[2021/45]
Inventor(s)01 / VENUGOPAL, Vivekanandan
Cupertino, CA, 95014 / US
02 / BHATIA, Ajay
Cupertino, CA, 95014 / US
03 / YE, Qi
Cupertino, CA, 95014 / US
 [2021/45]
Representative(s)Lang, Johannes
Bardehle Pagenberg Partnerschaft mbB
Patentanwälte, Rechtsanwälte
Prinzregentenplatz 7
81675 München / DE
[2021/45]
Application number, filing date21169462.520.04.2021
[2021/45]
Priority number, dateUS20201686630704.05.2020         Original published format: US202016866307
[2021/45]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP3907885
Date:10.11.2021
Language:EN
[2021/45]
Type: B1 Patent specification 
No.:EP3907885
Date:15.02.2023
Language:EN
[2023/07]
Search report(s)(Supplementary) European search report - dispatched on:EP30.09.2021
ClassificationIPC:H03K3/012, H03K3/037
[2021/45]
CPC:
H03K3/012 (EP,US); H03K5/135 (CN); H03K3/037 (EP,US);
Y02D10/00 (EP)
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2021/45]
TitleGerman:TAKTSCHWINGUNGSTOLERANTE SEQUENTIELLE SCHALTUNGEN MIT NIEDRIGER SPANNUNG ZUR DYNAMISCHEN LEISTUNGSEINSPARUNG[2021/45]
English:LOW VOLTAGE CLOCK SWING TOLERANT SEQUENTIAL CIRCUITS FOR DYNAMIC POWER SAVINGS[2022/39]
French:CIRCUITS SÉQUENTIELS TOLÉRANTS AUX OSCILLATIONS D'HORLOGE À BASSE TENSION POUR UNE ÉCONOMIE D'ÉNERGIE DYNAMIQUE[2021/45]
Former [2021/45]LOW VOLTAGE CLOCK SWING TOLERANT SEQUENTIAL CIRCUITS FOR DYNAMIC POWER SAVING
Examination procedure20.04.2021Examination requested  [2021/45]
22.04.2022Amendment by applicant (claims and/or description)
29.08.2022Communication of intention to grant the patent
03.01.2023Fee for grant paid
03.01.2023Fee for publishing/printing paid
03.01.2023Receipt of the translation of the claim(s)
Opposition(s)16.11.2023No opposition filed within time limit [2024/04]
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See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipAT15.02.2023
CZ15.02.2023
DK15.02.2023
EE15.02.2023
ES15.02.2023
FI15.02.2023
HR15.02.2023
IT15.02.2023
LT15.02.2023
LV15.02.2023
MC15.02.2023
NL15.02.2023
PL15.02.2023
RO15.02.2023
RS15.02.2023
SE15.02.2023
SI15.02.2023
SK15.02.2023
SM15.02.2023
IE20.04.2023
LU20.04.2023
BE30.04.2023
FR30.04.2023
NO15.05.2023
GR16.05.2023
IS15.06.2023
PT15.06.2023
[2024/27]
Former [2024/21]AT15.02.2023
CZ15.02.2023
DK15.02.2023
EE15.02.2023
ES15.02.2023
FI15.02.2023
HR15.02.2023
LT15.02.2023
LV15.02.2023
MC15.02.2023
NL15.02.2023
PL15.02.2023
RO15.02.2023
RS15.02.2023
SE15.02.2023
SI15.02.2023
SK15.02.2023
SM15.02.2023
IE20.04.2023
LU20.04.2023
BE30.04.2023
FR30.04.2023
NO15.05.2023
GR16.05.2023
IS15.06.2023
PT15.06.2023
Former [2024/11]AT15.02.2023
CZ15.02.2023
DK15.02.2023
EE15.02.2023
ES15.02.2023
FI15.02.2023
HR15.02.2023
LT15.02.2023
LV15.02.2023
MC15.02.2023
NL15.02.2023
PL15.02.2023
RO15.02.2023
RS15.02.2023
SE15.02.2023
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SK15.02.2023
SM15.02.2023
LU20.04.2023
BE30.04.2023
FR30.04.2023
NO15.05.2023
GR16.05.2023
IS15.06.2023
PT15.06.2023
Former [2024/08]AT15.02.2023
CZ15.02.2023
DK15.02.2023
EE15.02.2023
ES15.02.2023
FI15.02.2023
HR15.02.2023
LT15.02.2023
LV15.02.2023
MC15.02.2023
NL15.02.2023
PL15.02.2023
RO15.02.2023
RS15.02.2023
SE15.02.2023
SK15.02.2023
SM15.02.2023
LU20.04.2023
NO15.05.2023
GR16.05.2023
IS15.06.2023
PT15.06.2023
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CZ15.02.2023
DK15.02.2023
EE15.02.2023
ES15.02.2023
FI15.02.2023
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SM15.02.2023
LU20.04.2023
NO15.05.2023
GR16.05.2023
IS15.06.2023
PT15.06.2023
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DK15.02.2023
EE15.02.2023
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RO15.02.2023
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SK15.02.2023
SM15.02.2023
NO15.05.2023
GR16.05.2023
IS15.06.2023
PT15.06.2023
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DK15.02.2023
EE15.02.2023
ES15.02.2023
FI15.02.2023
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EE15.02.2023
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NL15.02.2023
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SE15.02.2023
SM15.02.2023
NO15.05.2023
GR16.05.2023
IS15.06.2023
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GR16.05.2023
IS15.06.2023
PT15.06.2023
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FI15.02.2023
HR15.02.2023
LT15.02.2023
LV15.02.2023
NL15.02.2023
PL15.02.2023
RS15.02.2023
SE15.02.2023
NO15.05.2023
GR16.05.2023
IS15.06.2023
PT15.06.2023
Former [2023/38]AT15.02.2023
ES15.02.2023
FI15.02.2023
HR15.02.2023
LT15.02.2023
LV15.02.2023
NL15.02.2023
PL15.02.2023
RS15.02.2023
SE15.02.2023
NO15.05.2023
GR16.05.2023
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FI15.02.2023
HR15.02.2023
LT15.02.2023
LV15.02.2023
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RS15.02.2023
SE15.02.2023
NO15.05.2023
GR16.05.2023
PT15.06.2023
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ES15.02.2023
FI15.02.2023
HR15.02.2023
LT15.02.2023
LV15.02.2023
NL15.02.2023
RS15.02.2023
SE15.02.2023
NO15.05.2023
PT15.06.2023
Former [2023/35]AT15.02.2023
ES15.02.2023
HR15.02.2023
LT15.02.2023
NL15.02.2023
RS15.02.2023
NO15.05.2023
PT15.06.2023
Former [2023/34]ES15.02.2023
LT15.02.2023
RS15.02.2023
PT15.06.2023
Former [2023/33]ES15.02.2023
LT15.02.2023
Documents cited:Search[A]US2013021078  (ELKIN ILYAS [US], et al) [A] 1-15 * abstract * * paragraphs [0002] , [0004] , [0008] , [0009] , [0034] - [0039] - [0067] *;
 [A]  - ZHANG YAN ET AL, "Low clock-swing conditional-precharge flip-flop for more than 30% power reduction", ELECTRONICS LETTERS, IEE STEVENAGE, GB, (20000427), vol. 36, no. 9, doi:10.1049/EL:20000491, ISSN 0013-5194, pages 785 - 786, XP006015145 [A] 1-15 * abstract * * page 1, column left * * page 2, column left, line 1 - line 5 *

DOI:   http://dx.doi.org/10.1049/el:20000491
 [A]  - LI X ET AL, "Self-blocking flip-flop design", ELECTRONICS LETTERS, IEE STEVENAGE, GB, (20120119), vol. 48, no. 2, doi:10.1049/EL.2011.2888, ISSN 0013-5194, pages 82 - 83, XP006040540 [A] 1,4-8,10-15 * abstract *

DOI:   http://dx.doi.org/10.1049/el.2011.2888
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.