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Extract from the Register of European Patents

EP About this file: EP4016642

EP4016642 - FABRICATION OF THIN FILM FIN TRANSISTOR STRUCTURE [Right-click to bookmark this link]
Status	Examination is in progress Status updated on 05.07.2024 Database last updated on 11.04.2026
Former	Request for examination was made Status updated on 30.12.2022
Former	The application has been published Status updated on 20.05.2022
Most recent event Tooltip	29.08.2025	New entry: Renewal fee paid
Applicant(s)	For all designated states Intel Corporation 2200 Mission College Boulevard Santa Clara, CA 95054 / US
	[2022/25]
Inventor(s)	01 / SATO, Noriyuki Hillsboro, 97124 / US
	02 / ATANASOV, Sarah Beaverton, 97003 / US
	03 / SHARMA, Abhishek Anil Portland, 97229 / US
	04 / SELL, Bernhard Portland, 97229 / US
	05 / KU, Chieh-Jen HILLSBORO, 97124 / US
	06 / TAN, Elliot Portland, 97201 / US
	07 / YOO, Hui Jae Hillsboro, 97124 / US
	08 / LAJOIE, Travis Forest Grove, 97116 / US
	09 / LE, Van Beaverton, 97007 / US
	10 / WANG, Pei-Hua Beaverton, 97006 / US
	11 / PECK, Jason Hillsboro, 97124 / US
	12 / BROWN-HEFT, Tobias Portland, 97201 / US
	[2022/25]
Representative(s)	2SPL Patentanwälte PartG mbB Landaubogen 3 81373 München / DE
	[2022/25]
Application number, filing date	21198468.7	23.09.2021
	[2022/25]
Priority number, date	US202017129867	21.12.2020 Original published format: US202017129867
	[2022/25]
Filing language	EN
Procedural language	EN
Publication	Type:	A1 Application with search report
	No.:	EP4016642
	Date:	22.06.2022
	Language:	EN
	[2022/25]
Search report(s)	(Supplementary) European search report - dispatched on:	EP	02.03.2022
Classification	IPC:	H01L29/66, H01L29/78	[2022/25]
	CPC:	H10D30/62 (EP,CN,KR); H10D30/024 (EP,CN,KR,US); H10D30/026 (EP); H10D30/611 (CN); H10D84/0158 (US); H10D84/038 (US); (+) H10D84/853 (US); H10W90/00 (KR) (-)
Designated contracting states	AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR [2023/05]
Former [2022/25]	AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR
Extension states	BA	Not yet paid
	ME	Not yet paid
Validation states	KH	Not yet paid
	MA	Not yet paid
	MD	Not yet paid
	TN	Not yet paid
Title	German:	HERSTELLUNG EINER DÜNNFILMTRANSISTORSTRUKTUR	[2022/25]
	English:	FABRICATION OF THIN FILM FIN TRANSISTOR STRUCTURE	[2022/25]
	French:	FABRICATION D'UNE STRUCTURE DE TRANSISTOR À AILETTES À FILM MINCE	[2022/25]
Examination procedure	21.12.2022	Amendment by applicant (claims and/or description)
	22.12.2022	Examination requested [2023/05]
	22.12.2022	Date on which the examining division has become responsible
	04.07.2024	Despatch of a communication from the examining division (Time limit: M04)
	15.10.2024	Reply to a communication from the examining division
Fees paid	Renewal fee
	29.08.2023	Renewal fee patent year 03
	29.08.2024	Renewal fee patent year 04
	28.08.2025	Renewal fee patent year 05
Opt-out from the exclusive Tooltip competence of the Unified Patent Court	See the Register of the Unified Patent Court for opt-out data
	Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:	Search	[XI] US5607865 (CHOI JONG M et al.) [X] 1,2,4-9,11-15 * the whole document *[I] 3,10
		[XA] US6069390 (HSU LOUIS LU-CHEN et al.) [X] 9-15 * column 3, line 16 - column 4, line 51; figures 1-3 *[A] 5
		[XI] US5309010 (KITAJIMA HIROSHI et al.) [X] 1,2,4,6-9,11-13,15 * column 7, line 15 - column 8, line 56; figures 3-7B *[I] 3,10
		[X] US2015303299 (CHANG HUNG-CHIH et al.) [X] 1-4,6,9,10,13,15 * paragraph [0045] - paragraph [0057]; figures 6A-11B *
		[X] US2015364592 (VAN DAL MARK et al.) [X] 1-4,6,9,13,15 * paragraph [0071] - paragraph [0072]; figures 25-29 * * paragraph [0037] * * paragraph [0041] *

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