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EP4154320
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EP About this file: EP4154320
| EP4154320 - METHOD FOR MAKING A SEMICONDUCTOR DEVICE USING SUPERLATTICES WITH DIFFERENT NON-SEMICONDUCTOR THERMAL STABILITIES [Right-click to bookmark this link] | Status | Request for examination was made Status updated on 24.02.2023 Database last updated on 14.09.2024 | |
| Former | The international publication has been made Status updated on 07.01.2022 | ||
| Former | unknown Status updated on 06.08.2021 | Most recent event Tooltip | 04.07.2024 | New entry: Renewal fee paid | Applicant(s) | For all designated states Atomera Incorporated 750 University Avenue, Suite 280 Los Gatos, CA 95032 / US | [2023/13] | Inventor(s) | 01 /
WEEKS, Keith Doran Chandler, Arizona 85224 / US | 02 /
CODY, Nyles Wynn Tempe, Arizona 85284 / US | 03 /
HYTHA, Marek Brookline, Massachusetts 02446 / US | 04 /
MEARS, Robert J. Wellesley, Massachusetts 02482 / US | [2023/13] | Representative(s) | Page White Farrer Bedford House 21a John Street London WC1N 2BF / GB | [N/P] |
| Former [2023/13] | Roberts, David, et al Page White & Farrer Limited Bedford House 21A John Street London WC1N 2BF / GB | Application number, filing date | 21746875.0 | 01.07.2021 | [2023/13] | WO2021US40088 | Priority number, date | US202063047365P | 02.07.2020 Original published format: US 202063047365 P | [2023/13] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | WO2022006396 | Date: | 06.01.2022 | Language: | EN | [2022/01] | Type: | A1 Application with search report | No.: | EP4154320 | Date: | 29.03.2023 | Language: | EN | The application published by WIPO in one of the EPO official languages on 06.01.2022 takes the place of the publication of the European patent application. | [2023/13] | Search report(s) | International search report - published on: | EP | 06.01.2022 | Classification | IPC: | H01L29/15, H01L21/02 | [2023/13] | CPC: |
H01L29/152 (EP);
H01L21/3225 (US);
H01L21/02507 (EP,US);
H01L21/02488 (EP)
| Designated contracting states | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR [2023/13] | Title | German: | VERFAHREN ZUR HERSTELLUNG EINER HALBLEITERANORDNUNG UNTER VERWENDUNG VON SUPERGITTERN MIT UNTERSCHIEDLICHER THERMISCHER STABILITÄT | [2023/13] | English: | METHOD FOR MAKING A SEMICONDUCTOR DEVICE USING SUPERLATTICES WITH DIFFERENT NON-SEMICONDUCTOR THERMAL STABILITIES | [2023/13] | French: | PROCÉDÉ DE FABRICATION D'UN DISPOSITIF À SEMI-CONDUCTEUR AU MOYEN DE SUPER-RÉSEAUX AYANT DES STABILITÉS THERMIQUES NON SEMI-CONDUCTRICES DIFFÉRENTES | [2023/13] | Entry into regional phase | 19.12.2022 | National basic fee paid | 19.12.2022 | Designation fee(s) paid | 19.12.2022 | Examination fee paid | Examination procedure | 28.04.2022 | Request for preliminary examination filed International Preliminary Examining Authority: EP | 19.12.2022 | Examination requested [2023/13] | 19.12.2022 | Date on which the examining division has become responsible | 28.06.2023 | Amendment by applicant (claims and/or description) | Fees paid | Renewal fee | 04.07.2023 | Renewal fee patent year 03 | 03.07.2024 | Renewal fee patent year 04 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Cited in | International search | [XYI]WO2015077580 (MEARS TECHNOLOGIES INC [US]) [X] 1,2,7,9-11,15 * paragraph [0053]; figures 5-8 * * paragraph [0054] * * paragraph [0036] - paragraph [0038] * [Y] 5,6,13,14,17-22 [I] 3,4,12,16; | [Y]US9558939 (STEPHENSON ROBERT [GB], et al) [Y] 5,6,13,14,17-22 * column 5, line 13 - line 61; figures 2, 3 ** column 8, line 52 - column 9, line 36; figure 7 *; | [XI]US2018040724 (MEARS ROBERT J [US], et al) [X] 1,7,9,10 * paragraph [0002]; figure 5A * * paragraph [0051] - paragraph [0060] * * paragraph [0078] * * paragraph [0091] * [I] 3,4,8; | [XI]US2019279869 (WEEKS KEITH DORAN [US], et al) [X] 1,7,9,10 * figures 5-12 * * paragraph [0056] - paragraph [0057] * * paragraph [0034] * [I] 3,4 | by applicant | US4937204 | US5216262 | US5357119 | US5683934 | GB2347520 | US6376337 | US6472685 | US2003034529 | US2003057416 | US7105895 | US10566191 | US2020135489 | US10811498 | US10818755 | - TSU, "Phenomena in silicon nanostructure devices", Applied Physics and Materials Science & Processing, (20000906), pages 391 - 402, XP002314003 | - LUO et al., "Chemical Design of Direct-Gap Light-Emitting Silicon", Physical Review Letters, (20020812), vol. 89, no. 7, doi:10.1103/PhysRevLett.89.076802, XP002314002 DOI: http://dx.doi.org/10.1103/PhysRevLett.89.076802 | US19600173308 |