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Extract from the Register of European Patents

EP About this file: EP4030731

EP4030731 - SYMMETRIC PATH/LINK OVER LAG INTERFACE USING LLDP FOR TIME SYNCHRONIZATION BETWEEN TWO NODES USING PTP [Right-click to bookmark this link]
StatusRequest for examination was made
Status updated on  20.01.2023
Database last updated on 11.09.2024
FormerThe application has been published
Status updated on  17.06.2022
Most recent event   Tooltip20.03.2024New entry: Renewal fee paid 
Applicant(s)For all designated states
Juniper Networks, Inc.
1133 Innovation Way
Sunnyvale, CA 94089 / US
[2022/29]
Inventor(s)01 / V.K, Prabhu Raj
560043 Bangalore / IN
02 / REDDY, M. Ramana
515641 Anantapur / IN
03 / GOPALAKRISHNAN, Kamatchi Soundaram
Dublin, 94568 / US
 [2022/29]
Representative(s)D Young & Co LLP
3 Noble Street
London EC2V 7BQ / GB
[N/P]
Former [2022/29]D Young & Co LLP
120 Holborn
London EC1N 2DY / GB
Application number, filing date22159590.325.03.2019
[2022/29]
Priority number, dateUS20181598290117.05.2018         Original published format: US201815982901
[2022/29]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP4030731
Date:20.07.2022
Language:EN
[2022/29]
Search report(s)(Supplementary) European search report - dispatched on:EP22.06.2022
ClassificationIPC:H04L45/24, H04J3/06
[2022/29]
CPC:
H04L45/245 (EP,US); H04J3/0667 (EP,CN,US); H04J3/0673 (US);
H04L41/12 (US); H04L47/24 (US); Y02D30/00 (EP);
Y02D30/50 (EP) (-)
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2023/08]
Former [2022/29]AL,  AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  HR,  HU,  IE,  IS,  IT,  LI,  LT,  LU,  LV,  MC,  MK,  MT,  NL,  NO,  PL,  PT,  RO,  RS,  SE,  SI,  SK,  SM,  TR 
TitleGerman:SYMMETRISCHER PFAD/SYMMETRISCHER LINK ÜBER KANALBÜNDELUNGSSCHNITTSTELLE UNTER VERWENDUNG VON LLDP ZUR ZEITSYNCHRONISATION ZWISCHEN ZWEI KNOTEN MIT PTP[2022/29]
English:SYMMETRIC PATH/LINK OVER LAG INTERFACE USING LLDP FOR TIME SYNCHRONIZATION BETWEEN TWO NODES USING PTP[2022/29]
French:TRAJET/LIAISON SYMÉTRIQUE SUR UNE INTERFACE DE DÉCALAGE UTILISANT LE PROTOCOLE LLDP POUR LA SYNCHRONISATION TEMPORELLE ENTRE DEUX N UDS UTILISANT LE PROTOCOLE PTP[2022/29]
Examination procedure17.01.2023Amendment by applicant (claims and/or description)
17.01.2023Examination requested  [2023/08]
17.01.2023Date on which the examining division has become responsible
Parent application(s)   TooltipEP19164816.1  / EP3570505
Fees paidRenewal fee
02.03.2022Renewal fee patent year 03
02.03.2022Renewal fee patent year 04
21.03.2023Renewal fee patent year 05
20.03.2024Renewal fee patent year 06
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[A]US2013336117  (YAN DESMOND [CA], et al) [A] 1-15 * paragraph [0002] - paragraph [0007] * * paragraph [0018] * * paragraph [0028] * * paragraph [0031] * * paragraph [0041] * * figure 4 *;
 [A]EP2701342  (ZTE CORP [CN]) [A] 1-15 * paragraph [0023] * * paragraph [0027] - paragraph [0028] * * paragraph [0045] - paragraph [0046] * * paragraph [0081] * * paragraph [0100] - paragraph [0101] * * figures 6,7 *;
 [A]US2015271088  (AO TING [CN]) [A] 1-15 * paragraph [0002] * * paragraph [0008] * * paragraph [0011] - paragraph [0012] * * paragraph [0025] * * paragraph [0044] - paragraph [0047] * * paragraph [0080] - paragraph [0083] * * figures 2,6 *;
 [A]US2016173216  (YANG QINGFENG [CN], et al) [A] 1-15 * paragraph [0012] * * paragraph [0029] - paragraph [0032] * * paragraph [0059] - paragraph [0064] * * paragraph [0097] - paragraph [0098] * * paragraph [0101] - paragraph [0104] ** figure 1 *
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.