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Extract from the Register of European Patents

EP About this file: EP4148775

EP4148775 - INTEGRATED CIRCUIT DEVICES INCLUDING A VIA AND METHODS OF FORMING THE SAME [Right-click to bookmark this link]
StatusThe patent has been granted
Status updated on  29.03.2024
Database last updated on 24.01.2025
FormerGrant of patent is intended
Status updated on  08.01.2024
FormerRequest for examination was made
Status updated on  10.02.2023
Most recent event   Tooltip24.01.2025Lapse of the patent in a contracting state
New state(s): EE
published on 26.02.2025 [2025/09]
Applicant(s)For all designated states
Samsung Electronics Co., Ltd.
129, Samsung-ro
Yeongtong-gu
Suwon-si, Gyeonggi-do 16677 / KR
[N/P]
Former [2023/11]For all designated states
Samsung Electronics Co., Ltd.
129, Samsung-ro
Yeongtong-gu, Suwon-si
Gyeonggi-do, 16677 / KR
Inventor(s)01 / LEE, Anthony Dongick
San Jose, CA 95134 / US
02 / SIMKA, Harsono
San Jose, CA 95134 / US
03 / HE, Ming
San Jose, CA 95134 / US
04 / NAM, Seowoo
San Jose, CA 95134 / US
05 / AHN, Sang Hoon
San Jose, CA 95134 / US
 [2023/11]
Representative(s)Kuhnen & Wacker Patent- und Rechtsanwaltsbüro PartG mbB
Prinz-Ludwig-Straße 40A
85354 Freising / DE
[2023/11]
Application number, filing date22178086.909.06.2022
[2023/11]
Priority number, dateUS202163242193P09.09.2021         Original published format: US 202163242193 P
US20211754647009.12.2021         Original published format: US202117546470
[2023/11]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP4148775
Date:15.03.2023
Language:EN
[2023/11]
Type: B1 Patent specification 
No.:EP4148775
Date:01.05.2024
Language:EN
[2024/18]
Search report(s)(Supplementary) European search report - dispatched on:EP01.12.2022
ClassificationIPC:H01L21/768, H01L23/522
[2023/11]
CPC:
H01L21/76885 (EP); H01L21/76895 (US); H01L21/31053 (US);
H01L21/31111 (US); H01L21/31144 (US); H01L21/76805 (US);
H01L21/76819 (US); H01L21/76829 (US); H01L21/76834 (EP);
H01L21/76897 (EP); H01L23/5226 (EP); H01L23/53242 (US);
H01L23/53257 (US); H01L23/535 (US) (-)
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2023/11]
TitleGerman:INTEGRIERTE SCHALTUNGSVORRICHTUNGEN MIT EINER DURCHKONTAKTIERUNG UND VERFAHREN ZU DEREN HERSTELLUNG[2023/11]
English:INTEGRATED CIRCUIT DEVICES INCLUDING A VIA AND METHODS OF FORMING THE SAME[2023/11]
French:DISPOSITIFS DE CIRCUIT INTÉGRÉS COMPRENANT UN TROU D'INTERCONNEXION ET LEURS PROCÉDÉS DE FORMATION[2023/11]
Examination procedure11.01.2023Amendment by applicant (claims and/or description)
11.01.2023Examination requested  [2023/11]
11.01.2023Date on which the examining division has become responsible
09.01.2024Communication of intention to grant the patent
25.03.2024Fee for grant paid
25.03.2024Fee for publishing/printing paid
25.03.2024Receipt of the translation of the claim(s)
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Patent Court
See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipAT01.05.2024
BG01.05.2024
DK01.05.2024
EE01.05.2024
ES01.05.2024
FI01.05.2024
HR01.05.2024
LV01.05.2024
PL01.05.2024
NO01.08.2024
RS01.08.2024
GR02.08.2024
IS01.09.2024
PT02.09.2024
[2025/09]
Former [2025/08]AT01.05.2024
BG01.05.2024
DK01.05.2024
ES01.05.2024
FI01.05.2024
HR01.05.2024
LV01.05.2024
PL01.05.2024
NO01.08.2024
RS01.08.2024
GR02.08.2024
IS01.09.2024
PT02.09.2024
Former [2024/50]AT01.05.2024
BG01.05.2024
ES01.05.2024
FI01.05.2024
HR01.05.2024
LV01.05.2024
PL01.05.2024
NO01.08.2024
RS01.08.2024
GR02.08.2024
IS01.09.2024
PT02.09.2024
Former [2024/48]AT01.05.2024
BG01.05.2024
ES01.05.2024
FI01.05.2024
HR01.05.2024
NO01.08.2024
GR02.08.2024
IS01.09.2024
PT02.09.2024
Documents cited:Search[X]US2014117558  (BOYANOV BOYAN [US]) [X] 16 * figure 3G *;
 [X]US2015130073  (SUNG SU-JENG [TW]) [X] 16 * figure 1 *;
 [X]US2019363048  (ZHAO LIE [US], et al) [X] 16 * figure 4 *;
 [X]US2020135560  (CLEVENGER LAWRENCE A [US], et al) [X] 16 * figure 7 *;
 [XI]US2021098264  (HUANG CHIEN-HUA [TW], et al) [X] 16,17 * paragraph [0028]; figure 1I * [I] 18;
 [XP]US2021375751  (DAI YU-TENG [TW], et al) [XP] 1-14,16 * figures 1,2,4-16 ** paragraph [0031]; figures 1, 2, 4-21 *
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.