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EP4195249
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EP About this file: EP4195249
| EP4195249 - INTEGRATED CIRCUIT STRUCTURES HAVING GATE CUT OFFSET [Right-click to bookmark this link] | Status | Request for examination was made Status updated on 22.12.2023 Database last updated on 02.11.2024 | |
| Former | The application has been published Status updated on 12.05.2023 | Most recent event Tooltip | 28.10.2024 | New entry: Renewal fee paid | Applicant(s) | For all designated states INTEL Corporation 2200 Mission College Blvd. Santa Clara, CA 95054 / US | [2023/24] | Inventor(s) | 01 /
YEMENICIOGLU, Sukru Portland, 97229 / US | 02 /
WANG, Xinning Hillsboro, 97124 / US | 03 /
GARDINER, Allen Portland, 97229 / US | 04 /
GHANI, Tahir Portland, 97229 / US | 05 /
HARAN, Mohit Hilsboro, 97124 / US | 06 /
GULER, Leonard P. Hillsboro, 97124 / US | [2023/24] | Representative(s) | 2SPL Patentanwälte PartG mbB Landaubogen 3 81373 München / DE | [2023/24] | Application number, filing date | 22206268.9 | 09.11.2022 | [2023/24] | Priority number, date | US202117549530 | 13.12.2021 Original published format: US202117549530 | [2023/24] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP4195249 | Date: | 14.06.2023 | Language: | EN | [2023/24] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 08.05.2023 | Classification | IPC: | H01L21/8234, H01L27/088, H01L29/06, H01L29/66, H01L29/775, H01L29/786 | [2023/24] | CPC: |
H01L21/823456 (EP);
H01L27/0886 (EP,CN);
H01L27/092 (US);
H01L21/02603 (US);
H01L21/823431 (EP,CN);
H01L21/823437 (CN);
H01L21/823481 (EP);
H01L21/823807 (US);
H01L21/823821 (CN);
H01L21/823828 (CN);
H01L21/823871 (US);
H01L27/0924 (CN);
H01L29/0673 (EP,US);
H01L29/42392 (EP,US);
H01L29/66439 (EP,US);
H01L29/66545 (EP,US);
H01L29/66553 (US);
H01L29/66742 (US);
| Designated contracting states | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, ME, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR [2024/04] |
| Former [2023/24] | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, ME, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR | Extension states | BA | Not yet paid | Validation states | KH | Not yet paid | MA | Not yet paid | MD | Not yet paid | TN | Not yet paid | Title | German: | INTEGRIERTE SCHALTUNGSSTRUKTUREN MIT GATE-CUT-OFFSET | [2023/24] | English: | INTEGRATED CIRCUIT STRUCTURES HAVING GATE CUT OFFSET | [2023/24] | French: | STRUCTURES DE CIRCUIT INTÉGRÉ AYANT UN DÉCALAGE DE COUPURE DE GRILLE | [2023/24] | Examination procedure | 28.11.2023 | Amendment by applicant (claims and/or description) | 14.12.2023 | Examination requested [2024/04] | 14.12.2023 | Date on which the examining division has become responsible | Fees paid | Renewal fee | 28.10.2024 | Renewal fee patent year 03 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]US2020020795 (BAO JUNJING [US], et al) [A] 1-15 * paragraphs [0010] , [0 11] ** figures 1A, 1B *; | [XYI]US2021020644 (PAUL BIPUL C [US], et al) [X] 15 * paragraphs [0004] , [0 32] - [0052] - [0 57] - [0060] - [0 64] * * figures 1-9, 13, 14 * [Y] 13 [I] 1-12,14; | [XAI]WO2021009579 (IBM [US], et al) [X] 15 * paragraphs [0027] , [0 29] , [0 58] - [0063] - [0 83] * * figures 1B, 11, 14 * [A] 13 [I] 1-12,14; | [Y]US2021305244 (BOUCHE GUILLAUME [US], et al) [Y] 13 * paragraphs [0040] - [0108] * * figures 40-42 * |