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Extract from the Register of European Patents

EP About this file: EP4276904

EP4276904 - ESD PROTECTION CIRCUIT, PROTECTION METHOD, SEMICONDUCTOR MEMORY, AND SYSTEM [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  13.03.2026
Database last updated on 28.03.2026
FormerThe patent has been granted
Status updated on  04.04.2025
FormerGrant of patent is intended
Status updated on  05.12.2024
FormerRequest for examination was made
Status updated on  13.10.2023
FormerThe international publication has been made
Status updated on  07.10.2023
Formerunknown
Status updated on  17.04.2023
Most recent event   Tooltip13.03.2026Lapse of the patent in a contracting state
New state(s): RO		published on 15.04.2026 [2026/16]
13.03.2026No opposition filed within time limitpublished on 15.04.2026 [2026/16]
Applicant(s)For all designated states
Changxin Memory Technologies, Inc.
No. 388, Xingye Avenue
Economic and Technological Development Area
Hefei, Anhui 230601 / CN
[2025/19]
Former [2023/46]For all designated states
Changxin Memory Technologies, Inc.
No. 388, Xingye Avenue
Economic and Technological Development Area
Hefei, Anhui 230601 / CN
Inventor(s)01 / XUE, Zhan
Hefei, Anhui 230601 / CN
02 / XU, Qian
Hefei, Anhui 230601 / CN
03 / YANG, Hang
Hefei, Anhui 230601 / CN
 [2025/02]
Former [2023/47]01 / XUE, Zhan
Hefei Anhui 230601 / CN
02 / XU, Qian
Hefei Anhui 230601 / CN
03 / YANG, Hang
Hefei Anhui 230601 / CN
Representative(s)Gulde & Partner
Patent- und Rechtsanwaltskanzlei mbB
Berliner Freiheit 2
10785 Berlin / DE
[2025/19]
Former [2023/46]V.O.
P.O. Box 87930
2508 DH Den Haag / NL
Application number, filing date22879561.317.06.2022
[2023/46]
WO2022CN99585
Priority number, dateCN20221034869501.04.2022         Original published format: CN202210348695
[2023/46]
Filing languageZH
Procedural languageEN
PublicationType: A1 Application with search report
No.:WO2023184721
Date:05.10.2023
Language:ZH
[2023/40]
Type: A1 Application with search report 
No.:EP4276904
Date:15.11.2023
Language:EN
[2023/46]
Type: B1 Patent specification 
No.:EP4276904
Date:07.05.2025
Language:EN
[2025/19]
Search report(s)International search report - published on:CN05.10.2023
(Supplementary) European search report - dispatched on:EP13.03.2024
ClassificationIPC:H01L27/02, // H01L29/78
[2024/15]
CPC:
H10D89/811 (EP,US); H10D30/601 (US); H10D62/126 (US);
H10D62/151 (US); H10D84/854 (US); H10D84/858 (US);
H10D89/813 (EP); H10D30/60 (EP); H10D30/603 (EP) (-)
Former IPC [2023/46]H01L27/02
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2023/46]
Extension statesBANot yet paid
MENot yet paid
Validation statesKHNot yet paid
MANot yet paid
MDNot yet paid
TNNot yet paid
TitleGerman:ESD-SCHUTZSCHALTUNG, SCHUTZVERFAHREN, HALBLEITERSPEICHER UND SYSTEM[2023/46]
English:ESD PROTECTION CIRCUIT, PROTECTION METHOD, SEMICONDUCTOR MEMORY, AND SYSTEM[2023/46]
French:CIRCUIT DE PROTECTION CONTRE LES DÉCHARGES ÉLECTROSTATIQUES, PROCÉDÉ DE PROTECTION, MÉMOIRE À SEMI-CONDUCTEURS ET SYSTÈME[2023/46]
Entry into regional phase17.04.2023Translation filed 
17.04.2023National basic fee paid 
17.04.2023Search fee paid 
17.04.2023Designation fee(s) paid 
17.04.2023Examination fee paid 
Examination procedure17.04.2023Examination requested  [2023/46]
30.09.2024Amendment by applicant (claims and/or description)
30.09.2024Date on which the examining division has become responsible
05.12.2024Communication of intention to grant the patent
28.03.2025Fee for grant paid
28.03.2025Fee for publishing/printing paid
28.03.2025Receipt of the translation of the claim(s)
Opposition(s)10.02.2026No opposition filed within time limit [2026/16]
Fees paidRenewal fee
31.03.2024Renewal fee patent year 03
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipAT07.05.2025
BG07.05.2025
CZ07.05.2025
DK07.05.2025
EE07.05.2025
ES07.05.2025
FI07.05.2025
HR07.05.2025
IT07.05.2025
LV07.05.2025
MC07.05.2025
NL07.05.2025
PL07.05.2025
RO07.05.2025
SK07.05.2025
SM07.05.2025
LU17.06.2025
NO07.08.2025
RS07.08.2025
GR08.08.2025
IS07.09.2025
PT08.09.2025
[2026/16]
Former [2026/14]AT07.05.2025
BG07.05.2025
CZ07.05.2025
DK07.05.2025
EE07.05.2025
ES07.05.2025
FI07.05.2025
HR07.05.2025
IT07.05.2025
LV07.05.2025
MC07.05.2025
NL07.05.2025
PL07.05.2025
SK07.05.2025
SM07.05.2025
LU17.06.2025
NO07.08.2025
RS07.08.2025
GR08.08.2025
IS07.09.2025
PT08.09.2025
Former [2026/13]AT07.05.2025
BG07.05.2025
CZ07.05.2025
DK07.05.2025
EE07.05.2025
ES07.05.2025
FI07.05.2025
HR07.05.2025
IT07.05.2025
LV07.05.2025
NL07.05.2025
PL07.05.2025
SK07.05.2025
SM07.05.2025
LU17.06.2025
NO07.08.2025
RS07.08.2025
GR08.08.2025
IS07.09.2025
PT08.09.2025
Former [2026/11]AT07.05.2025
BG07.05.2025
CZ07.05.2025
DK07.05.2025
EE07.05.2025
ES07.05.2025
FI07.05.2025
HR07.05.2025
IT07.05.2025
LV07.05.2025
NL07.05.2025
PL07.05.2025
SK07.05.2025
SM07.05.2025
NO07.08.2025
RS07.08.2025
GR08.08.2025
IS07.09.2025
PT08.09.2025
Former [2026/09]AT07.05.2025
BG07.05.2025
CZ07.05.2025
DK07.05.2025
ES07.05.2025
FI07.05.2025
HR07.05.2025
LV07.05.2025
NL07.05.2025
PL07.05.2025
SM07.05.2025
NO07.08.2025
RS07.08.2025
GR08.08.2025
IS07.09.2025
PT08.09.2025
Former [2025/49]AT07.05.2025
BG07.05.2025
ES07.05.2025
FI07.05.2025
HR07.05.2025
LV07.05.2025
NL07.05.2025
PL07.05.2025
NO07.08.2025
RS07.08.2025
GR08.08.2025
IS07.09.2025
PT08.09.2025
Former [2025/48]AT07.05.2025
BG07.05.2025
ES07.05.2025
FI07.05.2025
HR07.05.2025
NL07.05.2025
PL07.05.2025
NO07.08.2025
RS07.08.2025
GR08.08.2025
PT08.09.2025
Former [2025/47]BG07.05.2025
ES07.05.2025
FI07.05.2025
NL07.05.2025
PL07.05.2025
NO07.08.2025
GR08.08.2025
PT08.09.2025
Former [2025/46]ES07.05.2025
FI07.05.2025
PT08.09.2025
Documents cited:Search[XI] US2008151446  (KER MING-DOU et al.) [X] 1-9 * abstract; figure 16b * * paragraphs [0077] - [0080] *[I] 10-14
 [I] US2015229126  (DOMANSKI KRZYSZTOF et al.) [I] 1-14 * abstract; figure 3b * * paragraphs [0031] - [0033] *
 [XI]   MING-DOU KER ED - VASSILIS PALIOURAS ET AL: "ESD (Electrostatic Discharge) Protection Design for Nanoelectronics in CMOS Technology", COMMUNICATIONS, ADVANCED SIGNAL PROCESSING, CIRCUITS, AND SYSTEM DESIG N TECHNIQUES FOR, IEEE, PI, 1 May 2006 (2006-05-01), pages 217 - 279, XP031019018, ISBN: 978-1-4244-0460-5 [X] 1-9 * the whole document * [I] 10-14
 [XI]   VASSILEV V ET AL: "Snapback circuit model for cascoded NMOS ESD over-voltage protection structures", EUROPEAN SOLID-STATE DEVICE RESEARCH, 2003 33RD CONFERENCE ON. ESSDERC '03 SEPT. 16-18, 2003, PISCATAWAY, NJ, USA,IEEE, 16 September 2003 (2003-09-16), pages 561 - 564, XP032156313, ISBN: 978-0-7803-7999-2, DOI: 10.1109/ESSDERC.2003.1256938 [X] 1-9 * the whole document * [I] 10-14

DOI:   http://dx.doi.org/10.1109/ESSDERC.2003.1256938
International search[X] CN107564902  (ADVANCED ANALOG TECH INC et al.) [X] 1-14 * description, paragraphs [0028]-[0050], and figure 8 *
 [X] CN108054166  (UNIV JIANGNAN et al.) [X] 1-14 * description, paragraphs [0027]-[0042], and figures 1-3 *
 [A] US6514839  (KER MING-DOU et al.) [A] 1-14 * entire document *
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.