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EP0015342
European procedure
Extract from the Register of European Patents
EP About this file: EP0015342
| EP0015342 - Substrate bias regulator [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 18.01.1985 Database last updated on 26.07.2024 | Most recent event Tooltip | 19.03.1992 | Lapse of the patent in a contracting state | published on 06.05.1992 [1992/19] | Applicant(s) | For all designated states MOTOROLA, INC. 4350 East Camelback Road Suite 200F Phoenix, Arizona 85018 / US | [1980/19] | Inventor(s) | 01 /
Moench, Jerry Dale 11305 Spicewood Parkway Austin, Texas 78750 / US | 02 /
Tesch, Rodney Clair 11000 Blossom Bell Drive Austin, Texas 78759 / US | [1980/19] | Representative(s) | Newens, Leonard Eric, et al F.J. CLEVELAND & CO. 40/43 Chancery Lane London WC2A 1JQ / GB | [N/P] |
| Former [1980/19] | Newens, Leonard Eric, et al F.J. CLEVELAND & CO. 40/43 Chancery Lane London WC2A 1JQ / GB | Application number, filing date | 79302875.4 | 12.12.1979 | [1980/19] | Priority number, date | US19790017523 | 05.03.1979 Original published format: US 17523 | [1980/19] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0015342 | Date: | 17.09.1980 | Language: | EN | [1980/19] | Type: | B1 Patent specification | No.: | EP0015342 | Date: | 25.01.1984 | Language: | EN | [1984/04] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 19.06.1980 | Classification | IPC: | G05F3/20 | [1980/19] | CPC: |
G05F3/205 (EP)
| Designated contracting states | DE, FR, GB [1980/19] | Title | German: | Substrat-Vorspannungsregler | [1980/19] | English: | Substrate bias regulator | [1980/19] | French: | Régulateur de polarisation de substrat | [1980/19] | Examination procedure | 10.02.1981 | Examination requested [1981/16] | 21.05.1982 | Despatch of a communication from the examining division (Time limit: M04) | 24.08.1982 | Reply to a communication from the examining division | 22.09.1982 | Despatch of a communication from the examining division (Time limit: M02) | 09.10.1982 | Reply to a communication from the examining division | 18.04.1983 | Despatch of communication of intention to grant (Approval: ) | 15.07.1983 | Communication of intention to grant the patent | 25.07.1983 | Fee for grant paid | 25.07.1983 | Fee for publishing/printing paid | Opposition(s) | 26.10.1984 | No opposition filed within time limit [1985/12] | Fees paid | Renewal fee | 22.09.1981 | Renewal fee patent year 03 | 20.09.1982 | Renewal fee patent year 04 | 11.10.1983 | Renewal fee patent year 05 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | US3609414 [ ]; | FR2235417 [ ]; | US3913006 [ ]; | US4072890 [ ]; | US4049980 [ ] | [ ] - IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, Digest on Technical Papers, Vol. 19, February 18, 1976 New York US E. BLASER: "Substrate and Load Gate Voltage Compensation", pages 56 and 57. * The whole article * | [ ] - IBM TECHNICAL DISCLOSURE BULLETIN, Vol. 19, December 1976 New York US E. BLASER: "Substrate Compensation for Depletion-Mode FET Circuits", page 2530 and page 2531 * The whole article * | Examination | US4260909 |