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EP0028292
European procedure
Extract from the Register of European Patents
EP About this file: EP0028292
| EP0028292 - All-NPN transistor driver and logic circuit [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 12.04.1984 Database last updated on 28.03.2026 | Most recent event Tooltip | 12.04.1984 | No opposition filed within time limit | published on 13.06.1984 [1984/24] | Applicant(s) | For all designated states International Business Machines Corporation New Orchard Road Armonk, NY 10504 / US | [N/P] |
| Former [1981/19] | For all designated states International Business Machines Corporation Old Orchard Road Armonk, N.Y. 10504 / US | Inventor(s) | 01 /
Konian, Richard Robert 49 Brookland Farms Rd. Poughkeepsie, N.Y. 12601 / US | 02 /
Walsh, James Leo 23 South Drive Hyde Park, N.Y. 12538 / US | [1981/19] | Representative(s) | Neuland, Johannes IBM Deutschland GmbH Schönaicher Strasse 220 D-7030 Böblingen / DE | [N/P] |
| Former [1981/51] | Neuland, Johannes, Dipl.-Ing. IBM Deutschland GmbH Schönaicher Strasse 220 D-7030 Böblingen / DE | ||
| Former [1981/19] | Mönig, Anton, Dipl.-Ing. IBM Deutschland Informationssysteme GmbH, Patentwesen und Urheberrecht D-70548 Stuttgart / DE | Application number, filing date | 80104750.7 | 12.08.1980 | [1981/19] | Priority number, date | US19790082256 | 05.10.1979 Original published format: US 82256 | [1981/19] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0028292 | Date: | 13.05.1981 | Language: | EN | [1981/19] | Type: | B1 Patent specification | No.: | EP0028292 | Date: | 25.05.1983 | Language: | EN | [1983/21] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 06.03.1981 | Classification | IPC: | H03K5/02, H03K19/20 | [1981/19] | CPC: |
H03K17/625 (EP,US);
H03K19/086 (EP,US)
| Designated contracting states | DE, FR, GB, IT [1981/19] | Title | German: | Aus NPN-Transistoren aufgebaute Treiber- und Logikschaltung | [1981/19] | English: | All-NPN transistor driver and logic circuit | [1981/19] | French: | Etage d'attaque et circuit logique utilisant des transistors NPN | [1981/19] | Examination procedure | 09.10.1981 | Examination requested [1981/51] | 26.07.1982 | Despatch of communication of intention to grant (Approval: ) | 15.10.1982 | Communication of intention to grant the patent | 29.10.1982 | Fee for grant paid | 29.10.1982 | Fee for publishing/printing paid | Opposition(s) | 25.02.1984 | No opposition filed within time limit [1984/24] | Fees paid | Renewal fee | 19.08.1982 | Renewal fee patent year 03 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A] IBM TECHNICAL DISCLOSURE BULLETIN, Vol. 19, No. 7, December 1976, New York, J.R. McDOWELL et al. "Clock Driver for Integrated Circuit Loads", pages 2616 to 2617 [A] |