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EP0024720
European procedure
Extract from the Register of European Patents
EP About this file: EP0024720
| EP0024720 - Circuitry for processing data in a data processing system consisting of a central processor, a main memory and an interposed buffer memory [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 14.03.1986 Database last updated on 14.03.2026 | Most recent event Tooltip | 28.09.2007 | Lapse of the patent in a contracting state | published on 31.10.2007 [2007/44] | Applicant(s) | For all designated states SIEMENS AKTIENGESELLSCHAFT Werner-von-Siemens-Str. 1 DE-80333 München / DE | [N/P] |
| Former [1981/10] | For all designated states SIEMENS AKTIENGESELLSCHAFT Wittelsbacherplatz 2 D-80333 München / DE | Inventor(s) | 01 /
Kähler, Jürgen. Dipl.-Ing- Lampertstrasse 6 D-8031 Puchheim / DE | [1981/10] | Application number, filing date | 80105064.2 | 26.08.1980 | [1981/10] | Priority number, date | DE19792935135 | 30.08.1979 Original published format: DE 2935135 | [1981/10] | Filing language | DE | Procedural language | DE | Publication | Type: | A2 Application without search report | No.: | EP0024720 | Date: | 11.03.1981 | Language: | DE | [1981/10] | Type: | A3 Search report | No.: | EP0024720 | Date: | 11.08.1982 | Language: | DE | [1982/32] | Type: | B1 Patent specification | No.: | EP0024720 | Date: | 08.05.1985 | Language: | DE | [1985/19] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 10.06.1982 | Classification | IPC: | G06F13/00 | [1981/10] | CPC: |
G06F12/0891 (EP)
| Designated contracting states | AT, BE, CH, FR, GB, IT, LI, LU, NL, SE [1981/10] | Title | German: | Schaltungsanordnung zum Verarbeiten von Daten in einer aus Zentralprozessor, Arbeitsspeicher und dazwischen angeordnetem Pufferspeicher bestehenden Datenverarbeitungsanlage | [1981/10] | English: | Circuitry for processing data in a data processing system consisting of a central processor, a main memory and an interposed buffer memory | [1981/10] | French: | Circuits pour le traitement de données dans un système de traitement de données comprenant un processeur central, une mémoire de travail et une mémoire tampon intercalée | [1981/10] | File destroyed: | 15.01.2000 | Examination procedure | 28.10.1981 | Examination requested [1982/01] | 03.11.1983 | Despatch of a communication from the examining division (Time limit: M04) | 02.03.1984 | Reply to a communication from the examining division | 15.05.1984 | Despatch of a communication from the examining division (Time limit: M01) | 16.05.1984 | Reply to a communication from the examining division | 27.07.1984 | Despatch of communication of intention to grant (Approval: ) | 29.10.1984 | Communication of intention to grant the patent | 07.11.1984 | Fee for grant paid | 07.11.1984 | Fee for publishing/printing paid | Opposition(s) | 11.02.1986 | No opposition filed within time limit [1986/18] | Fees paid | Renewal fee | 26.08.1982 | Renewal fee patent year 03 | 26.08.1983 | Renewal fee patent year 04 | 24.08.1984 | Renewal fee patent year 05 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | IT | 08.05.1985 | LU | 31.08.1985 | [2007/44] |
| Former [1999/52] | IT | 08.05.1985 | |
| LU | 31.08.1985 | ||
| Former [1999/42] | IT | 08.05.1985 | Documents cited: | Search | [Y] IBM TECHNICAL DISCLOSURE BULLETIN, Band 13, Nr. 2, Juli 1970, Seiten 400-402, New York, USA M.W. BEE et al.: "Removal of failing buffer sections in a buffer-backing store" | [Y] IBM TECHNICAL DISCLOSURE BULLETIN, Band 13, Nr. 9, Februar 1971, Seiten 2777-2778, New York, USA P.A. SMITH: "Variable architecture computer" [Y] |