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Extract from the Register of European Patents

EP About this file: EP0031462

EP0031462 - Differential charge sensing system for a four device MTL memory cell [Right-click to bookmark this link]
Former [1981/27]Differential charge sensing system for an integrated memory using dual-capacitance cells coupled to two bit lines
[1984/10]
StatusNo opposition filed within time limit
Status updated on  08.01.1985
Database last updated on 22.08.2024
Most recent event   Tooltip28.09.2007Lapse of the patent in a contracting state
Updated state(s): SE
published on 31.10.2007  [2007/44]
Applicant(s)For all designated states
International Business Machines Corporation
New Orchard Road
Armonk, NY 10504 / US
[N/P]
Former [1981/27]For all designated states
International Business Machines Corporation
Old Orchard Road
Armonk, N.Y. 10504 / US
Inventor(s)01 / Gersbach, John Edwin
500 South Willard Street
Burlington Vermont 05401 / US
02 / Kim, Ick Whan
157 Browns River Road
Essex Junction Vermont 05452 / US
03 / Zehle, Adolf Mathias
Rte 2 North Hero
Grand Isle Vermont 05474 / US
[1981/27]
Representative(s)Lewit, Leonard
IBM Deutschland GmbH Schönaicher Strasse 220
D-7030 Böblingen / DE
[N/P]
Former [1981/27]Lewit, Leonard, Dipl.-Ing.
IBM Deutschland GmbH Schönaicher Strasse 220
D-7030 Böblingen / DE
Application number, filing date80107371.926.11.1980
[1981/27]
Priority number, dateUS1979010824327.12.1979         Original published format: US 108243
[1981/27]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0031462
Date:08.07.1981
Language:EN
[1981/27]
Type: A3 Search report 
No.:EP0031462
Date:05.08.1981
Language:EN
[1981/31]
Type: B1 Patent specification 
No.:EP0031462
Date:07.03.1984
Language:EN
[1984/10]
Search report(s)(Supplementary) European search report - dispatched on:EP04.06.1981
ClassificationIPC:G11C7/00, G11C11/40, G11C11/24
[1981/27]
CPC:
G11C11/4026 (EP,US); G11C11/4113 (EP,US); G11C11/413 (EP,US)
Designated contracting statesDE,   FR,   GB,   IT,   NL,   SE [1981/27]
TitleGerman:Differenzial Ladungslesesystem für eine aus 4 Teile bestehende MTL Speicherzelle[1984/10]
English:Differential charge sensing system for a four device MTL memory cell[1984/10]
French:Système de détection différentielle de charge pour un dispositif à 4 composants formant une cellule de mémoire MTL[1984/10]
Former [1981/27]Differenzial Ladungslesesystem für einen integrierten Speicher mit an zwei Bitleitungen gekoppelten Dualkondensator-Speicherzellen
Former [1981/27]Differential charge sensing system for an integrated memory using dual-capacitance cells coupled to two bit lines
Former [1981/27]Système de détection différentielle de charge pour une mémoire intégrée composée de cellules à deux capacités et réunies à deux lignes de bit
File destroyed:15.01.2000
Examination procedure28.08.1981Examination requested  [1981/45]
21.05.1982Despatch of a communication from the examining division (Time limit: M04)
14.09.1982Reply to a communication from the examining division
24.05.1983Despatch of communication of intention to grant (Approval: )
10.08.1983Communication of intention to grant the patent
21.10.1983Fee for grant paid
21.10.1983Fee for publishing/printing paid
Opposition(s)08.12.1984No opposition filed within time limit [1985/11]
Fees paidRenewal fee
16.11.1982Renewal fee patent year 03
22.11.1983Renewal fee patent year 04
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Lapses during opposition  TooltipIT07.03.1984
NL07.03.1984
SE07.03.1984
[2007/44]
Former [1999/42]SE07.03.1983
IT07.03.1984
NL07.03.1984
Former [1985/23]SE07.03.1983
NL07.03.1984
Former [1984/33]SE07.03.1983
Documents cited:Search[A]US3421026  (STOPPER HERBERT);
 US3540010  [ ] (HEIGHTLEY JOHN D, et al);
 [AD]US3815106  (WIEDMANN S);
 [A]US4023148  (HEUBER KLAUS, et al);
 US4032902  [ ] (HERNDON WILLIAM H);
 US4070656  [ ] (HEUBER KLAUS, et al);
 [A]US4090255  (BERGER HORST H, et al);
 US4110842  [ ] (SARKISSIAN VAHE A, et al);
 [P]EP0013302  (IBM [US]);
 [E]EP0021143  (IBM [US]);
 [E]EP0020995  (IBM [US])
    [ ] - IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. SC-2, No. 4, December 1967 New York, US J.E. IWERSEN et al. "Beam-lead sealed-junction semiconductor memory with minimal cell complexity", pages 196-201
    [ ] - IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. SC-13, No. 5, October 1978 New York, US KAWARADA et al. "A fast 7.5 ns access 1K-Bit RAM for cachememory systems", pages 656-663
 [P]  - IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, February 1980, New York, USA WIEDMANN et al. "A 16Kb static MTL/I2L memory chip", pages 222-223, 276.
 [A]  - IEEE SYMPOSIUM ON APPLICATIONS OF MICROELECTRONICS, Southampton, 21-23 September 1965, London, GB MATTHEWS: "Microelectronic integrated system cells", pages 30/1 to 30/24
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