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EP0018843
European procedure
Extract from the Register of European Patents
EP About this file: EP0018843
| EP0018843 - Semiconductor memory device with parallel output gating [Right-click to bookmark this link] | |||
| Former [1980/23] | Semiconductor, memory device parallel output gating | ||
| [1983/12] | Status | No opposition filed within time limit Status updated on 14.09.2016 Database last updated on 02.11.2024 | Most recent event Tooltip | 14.09.2016 | No opposition filed within time limit | Applicant(s) | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi Kanagawa 211 / JP | [N/P] |
| Former [1980/23] | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 / JP | Inventor(s) | 01 /
Miyasaka, Kiyoshi 577-45, Iijma-cho Totsuka-ku Yokohama-shi Kanagawa 244 / JP | [1980/23] | Representative(s) | Abbott, Leonard Charles, et al GILL JENNINGS & EVERY 53-64 Chancery Lane London WC2A 1HN / GB | [1980/23] | Application number, filing date | 80301456.2 | 02.05.1980 | [1980/23] | Priority number, date | JP19790054915 | 04.05.1979 Original published format: JP 5491579 | [1980/23] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0018843 | Date: | 12.11.1980 | Language: | EN | [1980/23] | Type: | B1 Patent specification | No.: | EP0018843 | Date: | 23.03.1983 | Language: | EN | [1983/12] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 08.09.1980 | Classification | IPC: | G06F13/00, G11C8/00, G11C11/24, G11C7/00 | [1980/23] | CPC: |
G11C7/1006 (EP,US);
G06F12/04 (EP,US);
G11C11/409 (EP,US);
G11C11/4096 (EP,US);
G11C11/419 (EP,US);
G11C8/04 (EP,US)
| Designated contracting states | DE, FR, GB, NL [1980/23] | Title | German: | Halbleiterspeichervorrichtung mit paralleler Ausgangssteuerung | [1980/23] | English: | Semiconductor memory device with parallel output gating | [1983/12] | French: | Dispositif de mémoire à semi-conducteurs avec portes de sortie parallèles | [1980/23] |
| Former [1980/23] | Semiconductor, memory device parallel output gating | Examination procedure | 13.05.1980 | Examination requested [1980/23] | 25.08.1981 | Despatch of a communication from the examining division (Time limit: M06) | 11.01.1982 | Reply to a communication from the examining division | 16.07.1982 | Despatch of communication of intention to grant (Approval: ) | 13.09.1982 | Communication of intention to grant the patent | 08.10.1982 | Fee for grant paid | 08.10.1982 | Fee for publishing/printing paid | Opposition(s) | 27.12.1983 | No opposition filed within time limit [ N /P ] | Fees paid | Renewal fee | 14.05.1982 | Renewal fee patent year 03 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | US4110842 [ ]; | US3613055 [ ] (VARADI ANDREW G, et al); | [A]US3771145 (WIENER P); | [A]US3836892 (DE SIMONE R, et al); | [X]US3857046 (RADOFF S, et al); | [A]US3895360 (CRICCHI JAMES RONALD, et al); | US3930239 [ ] (SALTERS ROELOF HERMAN WILLEM, et al); | [A]US4106109 (FASSBENDER CHARLES J); | [A]US4114192 (SUZUKI YASOJI, et al); | [A]US4120048 (FUHRMAN JAMES L) |