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Extract from the Register of European Patents

EP About this file: EP0054764

EP0054764 - A method of trimming the resistance of a semiconductor resistor device [Right-click to bookmark this link]
Former [1982/26]Semiconductor resistor device
[1987/38]
StatusNo opposition filed within time limit
Status updated on  19.07.1988
Database last updated on 24.08.2024
Most recent event   Tooltip19.07.1988No opposition filed within time limitpublished on 07.09.1988 [1988/36]
Applicant(s)For all designated states
Kabushiki Kaisha Toshiba
72, Horikawa-cho, Saiwai-ku Kawasaki-shi
Kanagawa-ken 210-8572 / JP
[N/P]
Former [1982/26]For all designated states
KABUSHIKI KAISHA TOSHIBA
72, Horikawa-cho, Saiwai-ku
Kawasaki-shi, Kanagawa-ken 210, Tokyo / JP
Inventor(s)01 / Komatsu, Shigeru
3-4-206, Iijima-danchi 527 Iijima-cho
Totsuka-ku Yokohama-shi / JP
[1982/26]
Representative(s)Kador & Partner Part mbB
Corneliusstraße 15
80469 München / DE
[N/P]
Former [1982/26]Kador & Partner
Corneliusstrasse 15
D-80469 München / DE
Application number, filing date81110017.130.11.1981
[1982/26]
Priority number, dateJP1980018132023.12.1980         Original published format: JP 18132080
[1982/26]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0054764
Date:30.06.1982
Language:EN
[1982/26]
Type: A3 Search report 
No.:EP0054764
Date:29.06.1983
Language:EN
[1983/26]
Type: B1 Patent specification 
No.:EP0054764
Date:16.09.1987
Language:EN
[1987/38]
Search report(s)(Supplementary) European search report - dispatched on:EP27.04.1983
ClassificationIPC:H01L29/86, H01L21/268
[1982/26]
CPC:
H01L21/268 (EP); H01L29/8605 (EP)
Designated contracting statesDE,   FR,   GB [1982/26]
TitleGerman:Verfahren zum Einstellen des Widerstandswertes einer Halbleiterwiderstandsanordnung[1987/38]
English:A method of trimming the resistance of a semiconductor resistor device[1987/38]
French:Procédé d'ajustage d'une résistance á semiconducteur[1987/38]
Former [1982/26]Halbleiterwiderstandsanordnung
Former [1982/26]Semiconductor resistor device
Former [1982/26]Dispositif de résistance à semiconducteur
Examination procedure30.11.1981Examination requested  [1982/26]
09.11.1984Despatch of a communication from the examining division (Time limit: M04)
12.03.1985Reply to a communication from the examining division
04.07.1985Despatch of a communication from the examining division (Time limit: M04)
31.10.1985Reply to a communication from the examining division
31.07.1986Despatch of communication of intention to grant (Approval: )
07.11.1986Communication of intention to grant the patent
21.01.1987Fee for grant paid
21.01.1987Fee for publishing/printing paid
Opposition(s)17.06.1988No opposition filed within time limit [1988/36]
Fees paidRenewal fee
16.08.1983Renewal fee patent year 03
05.10.1984Renewal fee patent year 04
26.11.1985Renewal fee patent year 05
26.11.1986Renewal fee patent year 06
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Documents cited:Search[A]DE2837315  ;
 [A]DE2849716  ;
 [A]US4179310
 [A]  - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 17, no. 10, March 1975, page 2878, New York (USA); J.A. PARISI: "Integrated resistor trimming".
 [A]  - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 21, no. 8, January 1979, pages 3271-3272, New York (USA); B.K. AGGARWAL: "Laser-programmable variable-value resistor".
 [A]  - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 21, no. 3, August 1978, pages 1124-1125, New York (USA); B.K. AGGARWAL: "Laser personalizable resistors".
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.