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EP0035326

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Extract from the Register of European Patents

EP About this file: EP0035326

EP0035326 - Decoder circuit [Right-click to bookmark this link]
Status	The application has been refused Status updated on 17.10.1985 Database last updated on 03.08.2024
Most recent event Tooltip	07.07.2007	Change - inventor	published on 08.08.2007 [2007/32]
Applicant(s)	For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi Kanagawa 211 / JP
	[N/P]
Former [1981/36]	For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 / JP
Inventor(s)	01 / Isogai, Hideaki 11-13, Minamisawa 4-chome Higashikurume-shi Tokyo 180-03 / JP
	[1981/36]
Representative(s)	Sunderland, James Harry, et al Haseltine Lake LLP Lincoln House 300 High Holborn London WC1V 7JH / GB
	[N/P]
Former [1981/36]	Sunderland, James Harry, et al HASELTINE LAKE & CO Hazlitt House 28 Southampton Buildings Chancery Lane London WC2A 1AT / GB
Application number, filing date	81300487.6	05.02.1981
	[1981/36]
Priority number, date	JP19800014576	08.02.1980 Original published format: JP 1457680
	[1981/36]
Filing language	EN
Procedural language	EN
Publication	Type:	A2 Application without search report
	No.:	EP0035326
	Date:	09.09.1981
	Language:	EN
	[1981/36]
	Type:	A3 Search report
	No.:	EP0035326
	Date:	23.09.1981
	Language:	EN
	[1981/38]
Search report(s)	(Supplementary) European search report - dispatched on:	EP	23.07.1981
Classification	IPC:	G11C8/00, G11C11/40, H03K13/25	[1981/36]
	CPC:	H03M7/005 (EP,US); G11C11/415 (EP,US); G11C8/10 (EP,US); G11C8/12 (EP,US)
Designated contracting states	DE, FR, GB, NL [1981/45]
Former [1981/36]	AT, BE, CH, DE, FR, GB, IT, LI, LU, NL, SE
Title	German:	Decoderschaltung	[1981/36]
	English:	Decoder circuit	[1981/36]
	French:	Circuit de décodage	[1981/36]
File destroyed:	13.07.1991
Examination procedure	01.06.1981	Despatch of communication of loss of particular rights: designated state(s) AT, BE, CH, IT, LU, SE
	12.08.1981	Loss of particular rights, legal effect: designated state(s)
	17.02.1982	Examination requested [1982/17]
	14.04.1983	Despatch of a communication from the examining division (Time limit: M06)
	17.10.1983	Reply to a communication from the examining division
	12.03.1984	Despatch of a communication from the examining division (Time limit: M08)
	20.09.1984	Reply to a communication from the examining division
	02.07.1985	Despatch of communication that the application is refused, reason: substantive examination [1985/51]
	12.07.1985	Application refused, date of legal effect [1985/51]
Fees paid	Renewal fee
	31.01.1983	Renewal fee patent year 03
	26.01.1984	Renewal fee patent year 04
	05.02.1985	Renewal fee patent year 05
	Penalty fee
	Penalty fee Rule 85a EPC 1973
	05.03.1981	AT M02 Not yet paid
	05.03.1981	BE M02 Not yet paid
	05.03.1981	CH M02 Not yet paid
	05.03.1981	IT M02 Not yet paid
	05.03.1981	LU M02 Not yet paid
	05.03.1981	SE M02 Not yet paid
Opt-out from the exclusive Tooltip competence of the Unified Patent Court	See the Register of the Unified Patent Court for opt-out data
	Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:	Search	[X]US3736574 (GERSBACH J);
		US4007451 [ ] (HEUBER KLAUS, et al);
		[P]EP0019988 (FUJITSU LTD [JP]);
		[P]DE2904457 (SIEMENS AG);
		[E]EP0024894 (FUJITSU LTD [JP]);
		[A]US4027285 (MILLHOLLAN MICHAEL S, et al);
		[A]DE2658523 (SIEMENS AG)
		[ ] - IEEE Transactions on Electron Devices, Vol. ED-26, No. 6, June 1979, pages 886-892 New York, U.S.A. K. KAWARADA et al.: "A 4K-Bit Static I2L Memory" * pages 889-890paragraph "D. New Decoder Circuit"; figures 6,7 *
		[ ] - IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 5, October 1979, pages 850-854 New York, U.S.A. H. GLOCK et al.: "An ECL 100K-Compatible 1024 X 4 Bit RAM with 15 ns Access Time" * pages 851-852paragraph "F Address Decoder"; figures 4,5
		[ ] - IEEE Journal of Solid-State Circuits, Vol. SC-15, No. 3, June 1980, pages 306-310 New YorkU.S.A. H. ERNST et al.: "A High-Speed ECL 100K Compatible 64 X 4 Bit RAM with 6 ns Access Time" * figure 2 *
		[ ] - Intel Data Sheet, December 1970, 15 pages, Intel Editor Mountain ViewU.S.A. "Partially Decoded Ramdom Access 265 Bit Bipolar Memory (3102) and Binary Decoder-Driver (3202)" * pages 1,10 *
		[ ] - IEEE International Solid-State Circuits Conference, 16th February 1978, pages 154-155 New YorkU.S.A. P.M. QUINN et al.: "A 16K x 113L Dynamic RAM"
		[ ] - IEEE Journal of Solid-State Circuits, Vol. SC-13, No. 5, October 1978, Pages 656-663 New YorkU.S.A. K. KAWARADA et al.: "A Fast 7.5 ns Access IK-Bit RAM for Cache-Memory Systems"

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