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Extract from the Register of European Patents

EP About this file: EP0094528

EP0094528 - Process for producing double-layer structures consisting of metal silicide and polysilicium on substrates containing integrated circuits by reactive ion etching [Right-click to bookmark this link]
StatusThe application has been withdrawn
Status updated on  20.12.1990
Database last updated on 25.09.2024
Most recent event   Tooltip07.07.2007Change - inventorpublished on 08.08.2007  [2007/32]
Applicant(s)For all designated states
SIEMENS AKTIENGESELLSCHAFT
Werner-von-Siemens-Str. 1
DE-80333 München / DE
[N/P]
Former [1983/47]For all designated states
SIEMENS AKTIENGESELLSCHAFT
Wittelsbacherplatz 2
D-80333 München / DE
Inventor(s)01 / Beinvogl, Willy, Dr.
Tutzinger Strasse 3
D-8000 München 70 / DE
[1983/47]
Application number, filing date83104121.527.04.1983
[1983/47]
Priority number, dateDE1982321682305.05.1982         Original published format: DE 3216823
[1983/47]
Filing languageDE
Procedural languageDE
PublicationType: A2 Application without search report 
No.:EP0094528
Date:23.11.1983
Language:DE
[1983/47]
Type: A3 Search report 
No.:EP0094528
Date:06.05.1987
Language:DE
[1987/19]
Search report(s)(Supplementary) European search report - dispatched on:EP18.03.1987
ClassificationIPC:H01L21/28, H01L21/90
[1983/47]
CPC:
H01L21/32137 (EP,US); H01L21/76889 (EP,US)
Designated contracting statesDE,   FR,   GB [1983/47]
TitleGerman:Verfahren zum Herstellen von Strukturen von aus Metallsilizid und Polysilizium bestehenden Doppelschichten auf integrierte Halbleiterschaltungen enthaltenden Substraten durch reaktives Ionenätzen[1983/47]
English:Process for producing double-layer structures consisting of metal silicide and polysilicium on substrates containing integrated circuits by reactive ion etching[1983/47]
French:Procédé pour la fabrication de structures à double couche comportant du silicide de métal et du polysilicium sur des substrats comportant des circuits intégrés par attaque chimique par ions réactifs[1983/47]
File destroyed:11.06.1996
Examination procedure19.11.1984Examination requested  [1985/05]
29.11.1989Despatch of a communication from the examining division (Time limit: M04)
17.04.1990Reply to a communication from the examining division
09.07.1990Despatch of a communication from the examining division (Time limit: M06)
12.12.1990Application withdrawn by applicant  [1991/06]
Request for further processing for:17.04.1990Request for further processing filed
17.04.1990Full payment received (date of receipt of payment)
Request granted
10.05.1990Decision despatched
Fees paidRenewal fee
26.04.1985Renewal fee patent year 03
28.04.1986Renewal fee patent year 04
24.04.1987Renewal fee patent year 05
25.04.1988Renewal fee patent year 06
25.04.1989Renewal fee patent year 07
25.04.1990Renewal fee patent year 08
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Documents cited:Search[X]JP5731140  ;
 [XP]GB2098931  (WESTERN ELECTRIC CO [US])
 [X]  - PATENTS ABSTRACTS OF JAPAN, Band 6, Nr. 99 (E-111)[977], 8. Juni 1982; & JP-A-57 31 140 (TOKYO SHIBAURA DENKI K.K.) 19-02-1982, & JP5731140 A 00000000
 [A]  - EXTENDED ABSTRACTS, Band 81-1, Mai 1981, Seiten 586-588, Pennington, New Jersey, US; W. BEINVOGL et al.: "Anisotropic etching of polysilicon and metal silicides in fluorine containing plasma"
 [A]  - EXTENDED ABSTRACTS, Band 81-2, Oktober 1981, Seiten 652-654, Pennington, New Jersey, US; W.W. YAO et al.: "Anisotropic polysilicon etching with Cl2 plasma"
 [A]  - JOURNAL OF THE ELECTROCHEMICAL SOCIETY, Band 128, Nr. 2, Februar 1981, Seiten 366-370, Manchester, New Hampshire, US; A.C. ADAMS et al.: "Edge profiles in the plasma etching of polycrystalline silicon"
 [A]  - SOLID STATE TECHNOLOGY, Band 25, Nr. 4, April 1982, Seiten 121-125, Port Washington, New York, US; E.C. WHITCOMB et al.: "Reactive ion etching of submicron MoSi2/poly-Si gates for CMOS/SOS devices"
 [XP]  - JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, Band 1, Nr. 1, Januar-März 1983, Seiten 15-22, American Vacuum Society, New York, US; H.J. MATTAUSCH et al.: "Reactive ion etching of Ta-silicide/polysilicon double layers for the fabrication of integrated circuits"
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