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EP0104765
European procedure
Extract from the Register of European Patents
EP About this file: EP0104765
| EP0104765 - Substrate structure of semiconductor device and method of manufacturing the same [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 18.04.1990 Database last updated on 16.09.2024 | Most recent event Tooltip | 18.04.1990 | No opposition filed within time limit | published on 06.06.1990 [1990/23] | Applicant(s) | For all designated states NIPPON TELEGRAPH AND TELEPHONE CORPORATION 1-6 Uchisaiwaicho 1-chome Chiyoda-ku Tokyo / JP | [1985/48] |
| Former [1984/14] | For all designated states Nippon Telegraph and Telephone Public Corporation 1-6 Uchisaiwai-cho 1-chome Chiyoda-ku Tokyo 100 / JP | Inventor(s) | 01 /
Sakuma, Kazuhito 1048, Kawaraguchi Ebina-shi Kanagawa-ken / JP | 02 /
Arita, Yoshinobu 861-1-8-506, Ishida Isehara-shi Kanagawa-ken / JP | 03 /
Sato, Masaaki 861-1-2-101, Ishida Isehara-shi Kanagawa-ken / JP | 04 /
Awaya, Nobuyoshi 2-183, Soubudai Zama-shi Kanagawa-ken / JP | [1984/14] | Representative(s) | Wood, Anthony Charles, et al Urquhart-Dykes & Lord 30 Welbeck Street London W1M 7PG / GB | [N/P] |
| Former [1989/26] | Wood, Anthony Charles, et al Urquhart-Dykes & Lord 91 Wimpole Street London W1M 8AH / GB | ||
| Former [1986/06] | Burnside, Michael Urquhart-Dykes & Lord 91 Wimpole Street London W1M 8AH / GB | ||
| Former [1985/48] | (deleted) | ||
| Former [1984/14] | Burnside, Michael, et al Urquhart-Dykes & Lord 91 Wimpole Street London W1M 8AH / GB | Application number, filing date | 83304898.6 | 24.08.1983 | [1984/14] | Priority number, date | JP19820145471 | 24.08.1982 Original published format: JP 14547182 | JP19830152482 | 23.08.1983 Original published format: JP 15248283 | [1984/14] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0104765 | Date: | 04.04.1984 | Language: | EN | [1984/14] | Type: | A3 Search report | No.: | EP0104765 | Date: | 09.07.1986 | Language: | EN | [1986/28] | Type: | B1 Patent specification | No.: | EP0104765 | Date: | 21.06.1989 | Language: | EN | [1989/25] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 22.05.1986 | Classification | IPC: | H01L21/76 | [1984/14] | CPC: |
H01L21/033 (EP);
H01L21/76 (KR);
H01L21/76229 (EP);
H01L21/76232 (EP)
| Designated contracting states | DE, FR, GB, NL [1984/14] | Title | German: | Substratstruktur für eine Halbleiteranordnung und Verfahren zur Herstellung dieses Substrats | [1984/14] | English: | Substrate structure of semiconductor device and method of manufacturing the same | [1984/14] | French: | Structure de substrat pour dispositif semi-conducteur et procédé pour la fabrication du substrat | [1984/14] | Examination procedure | 02.08.1986 | Examination requested [1986/41] | 16.11.1987 | Despatch of a communication from the examining division (Time limit: M06) | 24.05.1988 | Reply to a communication from the examining division | 13.09.1988 | Despatch of communication of intention to grant (Approval: Yes) | 22.12.1988 | Communication of intention to grant the patent | 21.02.1989 | Fee for grant paid | 21.02.1989 | Fee for publishing/printing paid | Opposition(s) | 22.03.1990 | No opposition filed within time limit [1990/23] | Fees paid | Renewal fee | 24.08.1985 | Renewal fee patent year 03 | 19.07.1986 | Renewal fee patent year 04 | 20.08.1987 | Renewal fee patent year 05 | 22.07.1988 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [Y]US4331708 (HUNTER WILLIAM R); | [A]US4269636 (RIVOLI ANTHONY L, et al) | [Y] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 24, no. 4, September 1981, pages 2185-2186, New York, US; G.R. GOTH et al.: "Prevention of defects in deep dielectric isolation trenches during oxidation" | [A] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 23, no. 4, September 1980, pages 1405-1408, New York, US; C.T. HORNG et al.: "Device isolation by using a narrow SiO2 trench" | [A] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 24, no. 11B, April 1982, pages 6008-6009, New York, US; B.M. KEMLAGE et al.: "Total dielectric isolation" | by applicant | US4269636 |