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EP0095418
European procedure
Extract from the Register of European Patents
EP About this file: EP0095418
| EP0095418 - Integrated logic circuit conceived in a manner such as to simplify its implantation on a substrate [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 29.05.1987 Database last updated on 24.08.2024 | Most recent event Tooltip | 29.05.1987 | No opposition filed within time limit | published on 15.07.1987 [1987/29] | Applicant(s) | For all designated states SOCIETE POUR L'ETUDE ET LA FABRICATION DE CIRCUITS INTEGRES SPECIAUX - E.F.C.I.S. 17, avenue des Martyrs F-38100 Grenoble / FR | [N/P] |
| Former [1983/48] | For all designated states SOCIETE POUR L'ETUDE ET LA FABRICATION DE CIRCUITS INTEGRES SPECIAUX - E.F.C.I.S. 17, avenue des Martyrs F-38100 Grenoble / FR | Inventor(s) | 01 /
Meyer, Jacques THOMSON-CSF SCPI 173, bld Haussmann F-75379 Paris Cedex 08 / FR | 02 /
Cru, Roger THOMSON-CSF SCPI 173, bld Haussmann F-75379 Paris Cedex 08 / FR | [1983/48] | Representative(s) | Guérin, Michel, et al Marks & Clerk France Conseils en Propriété Industrielle Immeuble Visium 22, Avenue Aristide Briand 94117 Arcueil Cedex / FR | [N/P] |
| Former [1983/48] | Guérin, Michel, et al THOMSON-CSF SCPI B.P. 329 50, rue Jean-Pierre Timbaud F-92402 Courbevoie Cédex / FR | Application number, filing date | 83401017.5 | 20.05.1983 | [1983/48] | Priority number, date | FR19820009052 | 25.05.1982 Original published format: FR 8209052 | [1983/48] | Filing language | FR | Procedural language | FR | Publication | Type: | A1 Application with search report | No.: | EP0095418 | Date: | 30.11.1983 | Language: | FR | [1983/48] | Type: | B1 Patent specification | No.: | EP0095418 | Date: | 30.07.1986 | Language: | FR | [1986/31] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 29.09.1983 | Classification | IPC: | H01L27/10, H03K19/177 | [1983/48] | CPC: |
H03K19/17708 (EP);
H10B20/00 (EP)
| Designated contracting states | CH, DE, FR, GB, LI, NL [1983/48] | Title | German: | Integrierter logischer Schaltkreis, der so ausgebildet ist, dass er auf einem Substrat einfach aufgebaut werden kann | [1983/48] | English: | Integrated logic circuit conceived in a manner such as to simplify its implantation on a substrate | [1983/48] | French: | Circuit intégré logique conçu de manière à simplifier son implantation sur un substrat | [1983/48] | Examination procedure | 12.12.1983 | Examination requested [1984/07] | 02.01.1985 | Despatch of a communication from the examining division (Time limit: M04) | 05.03.1985 | Reply to a communication from the examining division | 18.03.1985 | Despatch of a communication from the examining division (Time limit: M02) | 01.04.1985 | Reply to a communication from the examining division | 12.07.1985 | Despatch of communication of intention to grant (Approval: ) | 23.10.1985 | Communication of intention to grant the patent | 05.12.1985 | Fee for grant paid | 05.12.1985 | Fee for publishing/printing paid | Opposition(s) | 01.05.1987 | No opposition filed within time limit [1987/29] | Fees paid | Renewal fee | 20.04.1985 | Renewal fee patent year 03 | 18.04.1986 | Renewal fee patent year 04 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]FR2395647 (IBM [US]) | [A] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 19, no. 6, novembre 1976, pages 2303-2304, New York, USA | [A] - IEEE TRANSACTIONS ON COMPUTERS, vol. C-28, no. 9, septembre 1979, pages 594-601, New York, USA | [A] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 19, no. 6, novembre 1976, pages 2262-2265, New York, USA |