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EP0140369
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EP About this file: EP0140369
| EP0140369 - Semiconductor integrated circuit including series connected transistors [Right-click to bookmark this link] | Status | The application has been withdrawn Status updated on 01.09.1987 Database last updated on 02.11.2024 | Most recent event Tooltip | 15.08.2008 | Change - representative | published on 17.09.2008 [2008/38] | Applicant(s) | For all designated states Hitachi, Ltd. 6, Kanda Surugadai 4-chome Chiyoda-ku Tokyo / JP | [N/P] |
| Former [1985/19] | For all designated states HITACHI, LTD. 6, Kanda Surugadai 4-chome Chiyoda-ku, Tokyo 100 / JP | Inventor(s) | 01 /
Kaneko, Kenji 2609-11, Shimokuzawa Sagamihara-shi Kanagawa-ken / JP | 02 /
Nakamura, Tohru 6-6-16-614, Minami-machi Tanashi-shi Tokyo / JP | 03 /
Okabe, Takahiro 2196-36, Hinodemachi Hirai Nishitama-gun Tokyo / JP | 04 /
Nagata, Minoru 1558, Josuihoncho Kodaira-shi Tokyo / JP | [1985/19] | Representative(s) | Beetz & Partner mbB Patentanwälte Prinzregentenstraße 54 80538 München / DE | [N/P] |
| Former [2008/38] | Beetz & Partner Patentanwälte Steinsdorfstrasse 10 80538 München / DE | ||
| Former [1985/19] | Patentanwälte Beetz - Timpe - Siegfried Schmitt-Fumian - Mayr Steinsdorfstrasse 10 D-80538 München / DE | Application number, filing date | 84113062.8 | 30.10.1984 | [1985/19] | Priority number, date | JP19830204830 | 02.11.1983 Original published format: JP 20483083 | [1985/19] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0140369 | Date: | 08.05.1985 | Language: | EN | [1985/19] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 18.03.1985 | Classification | IPC: | H01L27/08 | [1985/19] | CPC: |
H01L27/0828 (EP);
H01L29/70 (KR);
H01L29/7327 (EP)
| Designated contracting states | DE, FR, GB, NL [1985/19] | Title | German: | Integrierte Halbleiterschaltung mit in Serien geschalteten Transistoren | [1985/19] | English: | Semiconductor integrated circuit including series connected transistors | [1985/19] | French: | Circuit intégré semi-conducteur comportant des transistors connectés en série | [1985/19] | File destroyed: | 24.05.1993 | Examination procedure | 13.05.1985 | Examination requested [1985/31] | 17.09.1986 | Despatch of a communication from the examining division (Time limit: M04) | 21.01.1987 | Reply to a communication from the examining division | 04.08.1987 | Despatch of communication of intention to grant (Approval: ) | 24.08.1987 | Application withdrawn by applicant [1987/43] | Fees paid | Renewal fee | 27.10.1986 | Renewal fee patent year 03 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [AD]DE3022565 (HITACHI LTD) | [X] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 12, no. 9, February 1970, page 1516, New York, US; H.D. VARADARAJAN: "Load impedance for transistor circuit" | [X] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 14, no. 6, November 1971, page 1684, New York, US; H. FRANTZ et al.: "Monolithic electric circuit" |