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EP0144759
European procedure
Extract from the Register of European Patents
EP About this file: EP0144759
| EP0144759 - Sample and hold circuit [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 14.05.1992 Database last updated on 19.07.2024 | Most recent event Tooltip | 05.10.2005 | Change: Appeal number | Applicant(s) | For all designated states Kabushiki Kaisha Toshiba 72, Horikawa-cho, Saiwai-ku Kawasaki-shi Kanagawa-ken 210-8572 / JP | [N/P] |
| Former [1985/25] | For all designated states KABUSHIKI KAISHA TOSHIBA 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210, Tokyo / JP | Inventor(s) | 01 /
Sugimoto, Yasuhiro c/o Patent Division KABUSHIKI KAISHA TOSHIBA 1-1 Shibaura 1-chome Minato-ku Tokyo 105 / JP | [1985/25] | Representative(s) | Henkel & Partner mbB Patentanwaltskanzlei, Rechtsanwaltskanzlei Maximiliansplatz 21 80333 München / DE | [N/P] |
| Former [1985/25] | Henkel, Feiler, Hänzel & Partner Möhlstrasse 37 D-81675 München / DE | Application number, filing date | 84113302.8 | 05.11.1984 | [1985/25] | Priority number, date | JP19830211879 | 11.11.1983 Original published format: JP 21187983 | [1985/25] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0144759 | Date: | 19.06.1985 | Language: | EN | [1985/25] | Type: | A3 Search report | No.: | EP0144759 | Date: | 01.10.1986 | Language: | EN | [1986/40] | Type: | B1 Patent specification | No.: | EP0144759 | Date: | 10.07.1991 | Language: | EN | [1991/28] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 13.08.1986 | Classification | IPC: | G11C27/02 | [1985/25] | CPC: |
G11C27/026 (EP,US)
| Designated contracting states | DE, FR, GB [1985/25] | Title | German: | Abtasthalteschaltung | [1985/29] | English: | Sample and hold circuit | [1985/25] | French: | Circuit d'échantillonnage et de maintien | [1985/29] | Examination procedure | 30.11.1984 | Examination requested [1985/25] | 13.01.1987 | Despatch of a communication from the examining division (Time limit: M04) | 20.11.1987 | Despatch of a communication from the examining division (Time limit: M06) | 26.05.1988 | Reply to a communication from the examining division | 09.12.1988 | Despatch of a communication from the examining division (Time limit: M06) | 28.06.1989 | Reply to a communication from the examining division | 26.02.1990 | Despatch of communication that the application is refused, reason: substantive examination {1} | 23.11.1990 | Despatch of communication of intention to grant (Approval: Yes) | 17.12.1990 | Communication of intention to grant the patent | 13.03.1991 | Fee for grant paid | 13.03.1991 | Fee for publishing/printing paid | Appeal following examination | 25.04.1990 | Appeal received No. T0550/90 | 26.06.1990 | Statement of grounds filed | 15.11.1990 | Result of appeal procedure: remittal for grant | Opposition(s) | 11.04.1992 | No opposition filed within time limit [1992/27] | Request for further processing for: | 28.06.1989 | Request for further processing filed | 28.06.1989 | Full payment received (date of receipt of payment) Request granted | 09.08.1989 | Decision despatched | Fees paid | Renewal fee | 25.11.1986 | Renewal fee patent year 03 | 14.11.1987 | Renewal fee patent year 04 | 14.11.1988 | Renewal fee patent year 05 | 09.11.1989 | Renewal fee patent year 06 | 20.11.1990 | Renewal fee patent year 07 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]US3412263 (BOYD WILLIAM R, et al); | [X]US3471719 (SMITH RICHARD); | [X]US3336518 (MURPHY ROBERT T) | [X] - ELECTRICAL DESIGN NEWS, vol. 28, no. 12, June 1983, pages 167-174, Boston, Massachusetts, US; H. BOLK: "Dual track/hold circuit improves data acquisition" | [A] - IEEE TRANSACTIONS ON COMMUNICATIONS, vol. COM-22, no. 7, July 1974, pages 986-994, New York, US; G.M. BENSON: "Thin-film auto-balance diode gate for voice-band sample and hold and resampler circuits" |