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EP0122659
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EP About this file: EP0122659
| EP0122659 - Method of manufacturing a high resistance layer having a low temperature coefficient of resistance and semiconductor device having such high resistance layer [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 12.06.1990 Database last updated on 14.09.2024 | Most recent event Tooltip | 07.07.2007 | Change - inventor | published on 08.08.2007 [2007/32] | Applicant(s) | For all designated states Koninklijke Philips Electronics N.V. Groenewoudseweg 1 5621 BA Eindhoven / NL | [N/P] |
| Former [1984/43] | For all designated states Philips Electronics N.V. Groenewoudseweg 1 NL-5621 BA Eindhoven / NL | Inventor(s) | 01 /
Arnold, Emil c/o INT. OCTROOIBUREAU B.V. Prof.Holstlaan 6 NL-5656 AA Eindhoven / NL | [1984/43] | Representative(s) | Rensen, Jan Geert, et al INTERNATIONAAL OCTROOIBUREAU B.V., Prof. Holstlaan 6 5656 AA Eindhoven / NL | [N/P] |
| Former [1988/31] | Rensen, Jan Geert, et al INTERNATIONAAL OCTROOIBUREAU B.V., Prof. Holstlaan 6 NL-5656 AA Eindhoven / NL | ||
| Former [1988/29] | Auwerda, Cornelis Petrus INTERNATIONAAL OCTROOIBUREAU B.V. Prof. Holstlaan 6 NL-5656 AA Eindhoven / NL | ||
| Former [1984/43] | Voorrips, Hugo Carel INTERNATIONAAL OCTROOIBUREAU B.V. Prof. Holstlaan 6 NL-5656 AA Eindhoven / NL | Application number, filing date | 84200465.7 | 03.04.1984 | [1984/43] | Priority number, date | US19830482671 | 06.04.1983 Original published format: US 482671 | [1984/43] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0122659 | Date: | 24.10.1984 | Language: | EN | [1984/43] | Type: | A3 Search report | No.: | EP0122659 | Date: | 28.01.1987 | Language: | EN | [1987/05] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 10.12.1986 | Classification | IPC: | H01L21/31 | [1984/43] | CPC: |
H01L28/20 (EP,US);
Y10T428/12674 (EP,US)
| Designated contracting states | DE, FR, GB, NL [1984/43] | Title | German: | Verfahren zur Herstellung einer hochresistenten Schicht mit niedrigem Temperaturkoeffizient und Halbleiteranordnung mit dieser hochresistenten Schicht | [1984/43] | English: | Method of manufacturing a high resistance layer having a low temperature coefficient of resistance and semiconductor device having such high resistance layer | [1984/43] | French: | Procédé pour la fabrication d'une couche à haute résistance ayant un coefficient de résistance bas et dispositif semi-conducteur ayant une telle couche à haute résistance | [1984/43] | File destroyed: | 12.06.1996 | Examination procedure | 25.05.1987 | Examination requested [1987/30] | 06.03.1989 | Despatch of a communication from the examining division (Time limit: M06) | 21.08.1989 | Reply to a communication from the examining division | 20.11.1989 | Despatch of a communication from the examining division (Time limit: M02) | 31.01.1990 | Application deemed to be withdrawn, date of legal effect [1990/31] | 06.03.1990 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time [1990/31] | Fees paid | Renewal fee | 18.04.1986 | Renewal fee patent year 03 | 15.04.1987 | Renewal fee patent year 04 | 20.04.1988 | Renewal fee patent year 05 | 25.04.1989 | Renewal fee patent year 06 | Penalty fee | Additional fee for renewal fee | 02.05.1990 | 07 M06 Not yet paid |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]JP56040269 ; | [A]FR2275886 (SONY CORP [JP]); | [AP]EP0101739 (HITACHI LTD [JP]) | [A] - EXTENDED ABSTRACTS, no. 79/1, May 1979, pages 447-449, abstract no. 168, Pennington, New York, US; H. YAMOTO et al.: "New technology by use of the doped SIPOS films" | [A] - PATENTS ABSTRACTS OF JAPAN, vol. 5, no. 95 (E-62)[767], 20th June 1981; & JP-A-56 040 269 (TOKYO SHIBAURA DENKI K.K.) 16-04-1981, & JP56040269 A 00000000 | [A] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 24, no. 4, September 1981, pages 2179,2180, New York, US; C.H. LEE: "Oxygen implantation for polysilicon resistor TCR optimization" |