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EP0134692
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EP About this file: EP0134692
| EP0134692 - Multilayer semiconductor devices with embedded conductor structure [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 25.04.1990 Database last updated on 31.08.2024 | Most recent event Tooltip | 31.07.2009 | Change - representative | published on 02.09.2009 [2009/36] | Applicant(s) | For all designated states Hitachi, Ltd. 6, Kanda Surugadai 4-chome Chiyoda-ku Tokyo / JP | [N/P] |
| Former [1985/12] | For all designated states HITACHI, LTD. 6, Kanda Surugadai 4-chome Chiyoda-ku, Tokyo 100 / JP | Inventor(s) | 01 /
Warabisako, Terunori 2196-143, Hirai Hinodemachi Nishitama-Gun Tokyo / JP | 02 /
Ohkura, Makoto 2-32-V407, Koyasu-Cho Hachioji-Shi Tokyo / JP | 03 /
Miyao, Masanobu 1188-5-107, Kamiarai Tokorozawa-Shi Saitama-Ken / JP | [1985/12] | Representative(s) | Calderbank, Thomas Roger, et al Mewburn Ellis LLP City Tower 40 Basinghall Street London EC2V 5DE / GB | [N/P] |
| Former [2009/36] | Calderbank, Thomas Roger, et al Mewburn Ellis LLP 33 Gutter Lane London EC2V 8AS / GB | ||
| Former [1985/12] | Calderbank, Thomas Roger, et al MEWBURN ELLIS York House 23 Kingsway London WC2B 6HP / GB | Application number, filing date | 84305165.7 | 30.07.1984 | [1985/12] | Priority number, date | JP19830150149 | 19.08.1983 Original published format: JP 15014983 | [1985/12] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0134692 | Date: | 20.03.1985 | Language: | EN | [1985/12] | Type: | A3 Search report | No.: | EP0134692 | Date: | 22.10.1986 | Language: | EN | [1986/43] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 02.09.1986 | Classification | IPC: | H01L23/48, H01L21/285, H01L23/52 | [1985/12] | CPC: |
H01L23/53271 (EP,US);
H01L27/00 (KR);
H01L23/5283 (EP,US);
H01L2924/0002 (EP,US)
| C-Set: |
H01L2924/0002, H01L2924/00 (EP,US)
| Designated contracting states | DE, FR, GB, NL [1985/12] | Title | German: | Mehrschicht-Halbleiteranordnungen mit einer eingebetteten Leiterstruktur | [1985/12] | English: | Multilayer semiconductor devices with embedded conductor structure | [1985/12] | French: | Dispositifs semi-conducteurs multi-couches ayant une structure conductrice enfoncée | [1985/12] | File destroyed: | 12.06.1996 | Examination procedure | 31.08.1984 | Examination requested [1985/12] | 01.08.1989 | Despatch of a communication from the examining division (Time limit: M04) | 12.12.1989 | Application deemed to be withdrawn, date of legal effect [1990/24] | 15.01.1990 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time [1990/24] | Fees paid | Renewal fee | 21.07.1986 | Renewal fee patent year 03 | 18.07.1987 | Renewal fee patent year 04 | 20.07.1988 | Renewal fee patent year 05 | 24.07.1989 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]EP0073487 (TOKYO SHIBAURA ELECTRIC CO [JP]); | [A]GB2077039 (XEROX CORP); | [A]EP0073509 (TOKYO SHIBAURA ELECTRIC CO [JP]); | [A]EP0076161 (FUJITSU LTD [JP]); | [A]EP0075945 (TOKYO SHIBAURA ELECTRIC CO [JP]); | [A]FR2496342 (TOKYO SHIBAURA ELECTRIC CO [JP], et al) | [A] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 22, no. 4, September 1979, pages 1462-1463, New York, US; M.A. BATTISTA et al.: "Logic masterslice design" |