-
EP0134731
European procedure
Extract from the Register of European Patents
EP About this file: EP0134731
| EP0134731 - Complementary logic integrated circuit [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 08.08.1989 Database last updated on 25.09.2024 | Most recent event Tooltip | 08.08.1989 | No opposition filed within time limit | published on 27.09.1989 [1989/39] | Applicant(s) | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi Kanagawa 211 / JP | [N/P] |
| Former [1985/12] | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 / JP | Inventor(s) | 01 /
Ohba, Osam 536-5-2-303, Ohmaru Inagi-shi Tokyo 206 / JP | 02 /
Tanizawa, Tetsu 7-1-301, Hosoyama 1 Chome Asao-ku Kawasaki-shi Kanagawa, 215 / JP | [1985/12] | Representative(s) | Descourtieux, Philippe, et al Cabinet Beau de Loménie 158, rue de l'Université 75340 Paris Cédex 07 / FR | [N/P] |
| Former [1985/12] | Descourtieux, Philippe, et al Cabinet Beau de Loménie 158, rue de l'Université F-75340 Paris Cédex 07 / FR | Application number, filing date | 84401438.1 | 06.07.1984 | [1985/12] | Priority number, date | JP19830123499 | 08.07.1983 Original published format: JP 12349983 | JP19830123500 | 08.07.1983 Original published format: JP 12350083 | [1985/12] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0134731 | Date: | 20.03.1985 | Language: | EN | [1985/12] | Type: | B1 Patent specification | No.: | EP0134731 | Date: | 12.10.1988 | Language: | EN | [1988/41] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 04.01.1985 | Classification | IPC: | H03K19/08, H03K19/094, H03K19/01, H03K19/003 | [1985/12] | CPC: |
H03K19/09448 (EP,US);
H03K19/001 (EP,US);
H03K19/0136 (EP,US)
| Designated contracting states | DE, FR, GB [1985/12] | Title | German: | Integrierte Komplementärlogikschaltung | [1985/12] | English: | Complementary logic integrated circuit | [1985/12] | French: | Circuit logique complémentaire intégré | [1985/12] | File destroyed: | 03.03.2001 | Examination procedure | 22.04.1985 | Examination requested [1985/27] | 24.03.1986 | Despatch of a communication from the examining division (Time limit: M04) | 26.06.1986 | Reply to a communication from the examining division | 25.08.1986 | Despatch of a communication from the examining division (Time limit: M04) | 30.10.1986 | Reply to a communication from the examining division | 13.05.1987 | Despatch of a communication from the examining division (Time limit: M04) | 31.08.1987 | Reply to a communication from the examining division | 10.02.1988 | Despatch of communication of intention to grant (Approval: Yes) | 07.04.1988 | Communication of intention to grant the patent | 16.06.1988 | Fee for grant paid | 16.06.1988 | Fee for publishing/printing paid | Opposition(s) | 13.07.1989 | No opposition filed within time limit [1989/39] | Fees paid | Renewal fee | 19.07.1986 | Renewal fee patent year 03 | 17.07.1987 | Renewal fee patent year 04 | 20.07.1988 | Renewal fee patent year 05 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [AD]US3879619 (PLESHKO PETER); | [A]GB2080651 (GEN ELECTRIC); | [A]US3649851 (COHEN BURTON E); | [A]US4021684 (MACEY FRANK G); | [A]US4103188 (MORTON GEORGE IRA); | [AP]EP0099100 (HITACHI LTD [JP]) |