-
EP0171105
European procedure
Extract from the Register of European Patents
EP About this file: EP0171105
| EP0171105 - Method of manufacturing a semiconductor device [Right-click to bookmark this link] | |||
| Former [1986/07] | Method of manufacturing a semiconductor device and device manufactured by the use of the method | ||
| [1990/24] | Status | No opposition filed within time limit Status updated on 13.04.1991 Database last updated on 14.09.2024 | Most recent event Tooltip | 13.04.1991 | No opposition filed within time limit | published on 05.06.1991 [1991/23] | Applicant(s) | For all designated states Koninklijke Philips Electronics N.V. Groenewoudseweg 1 5621 BA Eindhoven / NL | [N/P] |
| Former [1986/07] | For all designated states Philips Electronics N.V. Groenewoudseweg 1 NL-5621 BA Eindhoven / NL | Inventor(s) | 01 /
Maas, Henricus Godefridus Rafael c/o INT. OCTROOIBUREAU B.V. Prof. Holstlaan 6 NL-5656 AA Eindhoven / NL | 02 /
Slotboom, Jan Willem c/o INT. OCTROOIBUREAU B.V. Prof. Holstlaan 6 NL-5656 AA Eindhoven / NL | 03 /
Appels, Johannes Arnoldus c/o INT. OCTROOIBUREAU B.V. Prof. Holstlaan 6 NL-5656 AA Eindhoven / NL | 04 /
Osinksi, Kazimierz c/o INT. OCTROOIBUREAU B.V. Prof. Holstlaan 6 NL-5656 AA Eindhoven / NL | [1986/07] | Representative(s) | Houbiers, Ernest Emile M. G., et al INTERNATIONAAL OCTROOIBUREAU B.V., Prof. Holstlaan 6 5656 AA Eindhoven / NL | [N/P] |
| Former [1988/33] | Houbiers, Ernest Emile Marie Gerlach, et al INTERNATIONAAL OCTROOIBUREAU B.V., Prof. Holstlaan 6 NL-5656 AA Eindhoven / NL | ||
| Former [1988/29] | Auwerda, Cornelis Petrus INTERNATIONAAL OCTROOIBUREAU B.V. Prof. Holstlaan 6 NL-5656 AA Eindhoven / NL | ||
| Former [1986/07] | Voorrips, Hugo Carel INTERNATIONAAL OCTROOIBUREAU B.V. Prof. Holstlaan 6 NL-5656 AA Eindhoven / NL | Application number, filing date | 85201077.6 | 04.07.1985 | [1986/07] | Priority number, date | NL19840002223 | 13.07.1984 Original published format: NL 8402223 | [1986/07] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0171105 | Date: | 12.02.1986 | Language: | EN | [1986/07] | Type: | A3 Search report | No.: | EP0171105 | Date: | 19.02.1986 | Language: | EN | [1986/08] | Type: | B1 Patent specification | No.: | EP0171105 | Date: | 13.06.1990 | Language: | EN | [1990/24] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 18.12.1985 | Classification | IPC: | H01L21/28, H01L29/60 | [1986/07] | CPC: |
H01L29/66954 (EP,US);
H01L29/42396 (EP,US);
Y10S438/911 (EP,US)
| Designated contracting states | CH, DE, FR, GB, IT, LI, NL [1986/07] | Title | German: | Verfahren zur Herstellung einer Halbleiteranordnung | [1990/24] | English: | Method of manufacturing a semiconductor device | [1990/24] | French: | Procédé de fabrication d'un dispositif semi-conducteur | [1990/24] |
| Former [1986/07] | Verfahren zur Herstellung einer Halbleiteranordnung und nach diesem Verfahren hergestellte Anordnung | ||
| Former [1986/07] | Method of manufacturing a semiconductor device and device manufactured by the use of the method | ||
| Former [1986/07] | Procédé de fabrication d'un dispositif semi-conducteur et dispositif fabriqué selon ce procédé | Examination procedure | 14.08.1986 | Examination requested [1986/43] | 05.08.1988 | Despatch of a communication from the examining division (Time limit: M06) | 10.02.1989 | Reply to a communication from the examining division | 17.04.1989 | Despatch of a communication from the examining division (Time limit: M02) | 27.06.1989 | Reply to a communication from the examining division | 28.07.1989 | Despatch of communication of intention to grant (Approval: Yes) | 08.12.1989 | Communication of intention to grant the patent | 12.03.1990 | Fee for grant paid | 12.03.1990 | Fee for publishing/printing paid | Opposition(s) | 14.03.1991 | No opposition filed within time limit [1991/23] | Fees paid | Renewal fee | 13.07.1987 | Renewal fee patent year 03 | 19.07.1988 | Renewal fee patent year 04 | 14.07.1989 | Renewal fee patent year 05 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [E]EP0158371 (PHILIPS NV [NL]); | [P]EP0132009 (PHILIPS NV [NL]); | [A]EP0098652 (PHILIPS NV [NL]) | [A] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 24, no. 11a, April 1982, pages 5581-5584, New York, US; S.D. MALAVIYA: "High desity, high performance FET process and structure" | [A] - IEEE ELECTRON DEVICE LETTERS, vol.EDL-2, no. 4, April 1981, pages 92-94, IEEE, New York, US; V.J. KAPOOR: "Charge-coupled devices with submicron gaps" | [A] - IBM JOURNAL RESEARCH DEVELOPMENT, vol. 24, no. 3, May 1980, pages 339-347, New York, US; V.L. RIDEOUT et al.: "A one-device memory cell using a single layer of polysilicon and a self-registering metal-to-polysilicon contact" | [A] - IEDM WASHINGTON, 8th-10th December 1980, pages 760-763, IEEE, New York, US; F.Z. CUSTODE et al.: "VLSI-A totally self-aligned MOS transistor" |