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Extract from the Register of European Patents

EP About this file: EP0185412

EP0185412 - Circuit arrangement for reducing the occurrence of spurious signals on an output of an electronic circuit when the circuit power supply is switched on and off [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  22.11.1990
Database last updated on 03.10.2024
Most recent event   Tooltip23.02.1991Lapse of the patent in a contracting state
New state(s): BE
published on 17.04.1991 [1991/16]
Applicant(s)For all designated states
Koninklijke Philips Electronics N.V.
Groenewoudseweg 1
5621 BA Eindhoven / NL
[N/P]
Former [1986/26]For all designated states
Philips Electronics N.V.
Groenewoudseweg 1
NL-5621 BA Eindhoven / NL
Inventor(s)01 / Dijkmans, Eise Carel
c/o INT. OCTROOIBUREAU B.V. Prof. Holstlaan 6
NL-5656 AA Eindhoven / NL
[1986/26]
Representative(s)Peters, Rudolf Johannes, et al
Philips Intellectual Property & Standards
High Tech Campus 5
5656 AE Eindhoven / NL
[N/P]
Former [1986/26]Peters, Rudolf Johannes, et al
INTERNATIONAAL OCTROOIBUREAU B.V., Prof. Holstlaan 6
NL-5656 AA Eindhoven / NL
Application number, filing date85201916.521.11.1985
[1986/26]
Priority number, dateNL1984000382017.12.1984         Original published format: NL 8403820
[1986/26]
Filing languageNL
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP0185412
Date:25.06.1986
Language:EN
[1986/26]
Type: B1 Patent specification 
No.:EP0185412
Date:31.01.1990
Language:EN
[1990/05]
Search report(s)(Supplementary) European search report - dispatched on:EP10.04.1986
ClassificationIPC:H03F1/30, H03K17/28
[1986/26]
CPC:
H03F1/305 (EP,US); H03K17/60 (KR); H03K17/28 (EP,US)
Designated contracting statesBE,   DE,   FR,   GB,   IT,   NL [1986/26]
TitleGerman:Schaltungsvorrichtung zur Verminderung von Fehlersignalen am Ausgang einer elektronischen Schaltung beim Ein- und Ausschalten der Versorgungsspannungsquelle[1986/26]
English:Circuit arrangement for reducing the occurrence of spurious signals on an output of an electronic circuit when the circuit power supply is switched on and off[1986/26]
French:Montage pour réduire l'occurence de signaux parasites à la sortie d'un circuit électronique quand le circuit d'alimentation est enclenché et déclenché[1986/26]
Examination procedure22.12.1986Examination requested  [1987/11]
02.01.1989Despatch of communication of intention to grant (Approval: Yes)
14.07.1989Communication of intention to grant the patent
16.10.1989Fee for grant paid
16.10.1989Fee for publishing/printing paid
Opposition(s)01.11.1990No opposition filed within time limit [1991/02]
Fees paidRenewal fee
13.11.1987Renewal fee patent year 03
28.11.1988Renewal fee patent year 04
27.11.1989Renewal fee patent year 05
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Lapses during opposition  TooltipBE31.01.1990
NL31.01.1990
[1991/16]
Former [1990/44]NL31.01.1990
Documents cited:Search[A]JP5545250  ;
 [Y]US4180750  (ITO HIDEO [JP], et al);
 [Y]EP0096944  (PHILIPS PATENTVERWALTUNG [DE], et al);
 [A]US3943385  (ACHTSTAETTER GERHARD)
 [A]  - RADIO FERNSEHEN ELEKTRONIK, vol. 27, no. 10, October 1978, pages 621-625, Berlin, DD; H.-E. KRÖBEL: "Grundschaltungen der Analogen integrierten Technik"
 [A]  - PATENTS ABSTRACT OF JAPAN, vol. 4, no. 79, 7th June 1980, page 24 E 14; & JP - A - 55 45 250 (TOKYO SHIBAURA DENKI K.K.) 29-03-1980, & JP5545250 A 00000000
ExaminationUS4371841
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.