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EP0174845
European procedure
Extract from the Register of European Patents
EP About this file: EP0174845
| EP0174845 - Semiconductor memory device [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 27.05.1993 Database last updated on 03.10.2024 | Most recent event Tooltip | 27.05.1993 | No opposition filed within time limit | published on 14.07.1993 [1993/28] | Applicant(s) | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi Kanagawa 211 / JP | [N/P] |
| Former [1986/12] | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 / JP | Inventor(s) | 01 /
Takemae, Yoshihiro 8-13-24-303, Akasaka Minato-ku Tokyo 107 / JP | [1986/12] | Representative(s) | Fane, Christopher Robin King, et al Haseltine Lake & Co., Imperial House, 15-19 Kingsway London WC2B 6UD / GB | [N/P] |
| Former [1986/12] | Fane, Christopher Robin King, et al HASELTINE LAKE & CO. Hazlitt House 28 Southampton Buildings Chancery Lane London, WC2A 1AT / GB | Application number, filing date | 85306464.0 | 11.09.1985 | [1986/12] | Priority number, date | JP19840188891 | 11.09.1984 Original published format: JP 18889184 | [1986/12] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0174845 | Date: | 19.03.1986 | Language: | EN | [1986/12] | Type: | A3 Search report | No.: | EP0174845 | Date: | 16.08.1989 | Language: | EN | [1989/33] | Type: | B1 Patent specification | No.: | EP0174845 | Date: | 22.07.1992 | Language: | EN | [1992/30] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 26.06.1989 | Classification | IPC: | G11C8/00 | [1986/12] | CPC: |
G11C7/1036 (EP,US);
H01L27/00 (KR);
G11C7/10 (EP,US);
G11C7/22 (EP,US);
G11C8/00 (KR);
G11C8/04 (EP,US);
G11C8/10 (EP,US)
(-)
| Designated contracting states | DE, FR, GB [1986/12] | Title | German: | Halbleiterspeicheranordnung | [1986/12] | English: | Semiconductor memory device | [1986/12] | French: | Dispositif de mémoire semi-conductrice | [1986/12] | Examination procedure | 28.11.1989 | Examination requested [1990/04] | 10.09.1990 | Despatch of a communication from the examining division (Time limit: M06) | 22.04.1991 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time | 02.07.1991 | Reply to a communication from the examining division | 19.09.1991 | Despatch of communication of intention to grant (Approval: No) | 21.01.1992 | Despatch of communication of intention to grant (Approval: later approval) | 29.01.1992 | Communication of intention to grant the patent | 21.04.1992 | Fee for grant paid | 21.04.1992 | Fee for publishing/printing paid | Opposition(s) | 23.04.1993 | No opposition filed within time limit [1993/28] | Request for further processing for: | 02.07.1991 | Request for further processing filed | 04.06.1991 | Full payment received (date of receipt of payment) Request granted | 16.07.1991 | Decision despatched | Fees paid | Renewal fee | 03.09.1987 | Renewal fee patent year 03 | 02.09.1988 | Renewal fee patent year 04 | 01.09.1989 | Renewal fee patent year 05 | 07.09.1990 | Renewal fee patent year 06 | 02.09.1991 | Renewal fee patent year 07 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]US4044339 (BERG ROBERT O); | [X]EP0045063 (NEC CORP [JP]); | [A]US4321695 (REDWINE DONALD J, et al); | [A]EP0115128 (FUJITSU LTD [JP]); | [A]EP0115187 (FUJITSU LTD [JP]); | [X] - FUJISHIMA K, ET AL., "A 256K DYNAMIC RAM WITH PAGE-NIBBLE MODE", IEEE JOURNAL OF SOLID-STATE CIRCUITS., IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, PISCATAWAY, NJ, USA, (19831001), vol. SC-18, no. 05, doi:10.1109/JSSC.1983.1051980, ISSN 0018-9200, pages 470 - 478, XP000819395 DOI: http://dx.doi.org/10.1109/JSSC.1983.1051980 | Examination | JPS59135695 | US4586167 | - IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. SC-18, no. 5, October 1983, pages 470-478; IEEE, New York, US, K. FUJISHIMA et al.: "A 256K dynamic RAM with page-nibble mode", page 472, left-hand column, line 35 - right-hand column, line 12 |