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Extract from the Register of European Patents

EP About this file: EP0177336

EP0177336 - Gate array integrated device [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  27.05.1993
Database last updated on 24.08.2024
Most recent event   Tooltip27.05.1993No opposition filed within time limitpublished on 14.07.1993 [1993/28]
Applicant(s)For all designated states
FUJITSU LIMITED
1015, Kamikodanaka, Nakahara-ku Kawasaki-shi
Kanagawa 211 / JP
[N/P]
Former [1986/15]For all designated states
FUJITSU LIMITED
1015, Kamikodanaka, Nakahara-ku
Kawasaki-shi, Kanagawa 211 / JP
Inventor(s)01 / Takayama, Yoshihisa
Sasamoto-so A-2 1292, Kamikodanaka Nakahara-ku
Kawasaki-shi Kanagawa 211 / JP
02 / Kawauchi, Kazuyuki
4-1-54-301, Shimoda-cho Kohoku-ku
Yokohama-shi Kanagawa 223 / JP
03 / Fujii, Shigeru
27-6-403, Kirigaoka 5-chome Midori-ku
Yokohama-shi Kanagawa 227 / JP
04 / Yoshida, Toshihiko
Copo Narushisu A201 2-7-7, Shinishikawa Midori-ku
Yokohama-shi Kanagawa 227 / JP
[1992/30]
Former [1986/15]01 / Takayama, Yoshihisa
Sasamoto-so A-2 1292, Kamikodanaka Nakahara-ku
Kawasaki-shi Kanagawa 211 / JP
02 / Kawauchi, Kazuyuki
4-1-54-301, Shimoda-cho Kohoku-ku
Yokohama-shi Kanagawa 223 / JP
03 / Fujii, Shigeru
27-6-403, Kirigaoka 5-chome Midori-ku
Yokohama-shi Kanagawa 227 / JP
04 / Yoshida, Toshihiko
Copo Narushisu A201 2-7-7, Shinisikawa Midori-ku
Yokohama-shi Kanagawa 227 / JP
Representative(s)Rackham, Stephen Neil, et al
Gill Jennings & Every LLP Broadgate House 7 Eldon Street
London EC2M 7LH / GB
[N/P]
Former [1986/15]Rackham, Stephen Neil, et al
GILL JENNINGS & EVERY, Broadgate House, 7 Eldon Street
London EC2M 7LH / GB
Application number, filing date85307023.301.10.1985
[1986/15]
Priority number, dateJP1984020614403.10.1984         Original published format: JP 20614484
JP1984022044722.10.1984         Original published format: JP 22044784
JP1984022045022.10.1984         Original published format: JP 22045084
JP1984027450428.12.1984         Original published format: JP 27450484
[1986/15]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0177336
Date:09.04.1986
Language:EN
[1986/15]
Type: A3 Search report 
No.:EP0177336
Date:15.04.1987
Language:EN
[1987/16]
Type: B1 Patent specification 
No.:EP0177336
Date:22.07.1992
Language:EN
[1992/30]
Search report(s)(Supplementary) European search report - dispatched on:EP24.02.1987
ClassificationIPC:H01L27/02
[1986/15]
CPC:
H01L27/092 (EP,KR,US); H01L27/11807 (EP,KR,US); H01L21/8238 (KR);
H01L23/528 (EP,US); H01L27/0207 (KR); H01L27/0218 (EP,US);
H10B41/35 (KR); H01L2924/0002 (EP,US); H01L2924/3011 (EP,US) (-)
C-Set:
H01L2924/0002, H01L2924/00 (EP,US)
Designated contracting statesDE,   FR,   GB [1986/15]
TitleGerman:Integrierte Gate-Matrixstruktur[1986/15]
English:Gate array integrated device[1986/15]
French:Structure intégrée de matrice de portes[1986/15]
Examination procedure04.09.1987Examination requested  [1987/45]
20.07.1990Despatch of a communication from the examining division (Time limit: M06)
24.01.1991Reply to a communication from the examining division
11.10.1991Despatch of communication of intention to grant (Approval: Yes)
27.01.1992Communication of intention to grant the patent
22.04.1992Fee for grant paid
22.04.1992Fee for publishing/printing paid
Opposition(s)23.04.1993No opposition filed within time limit [1993/28]
Fees paidRenewal fee
19.10.1987Renewal fee patent year 03
21.10.1988Renewal fee patent year 04
09.10.1989Renewal fee patent year 05
12.10.1990Renewal fee patent year 06
10.10.1991Renewal fee patent year 07
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Documents cited:Search[A]JP59163837  ;
 [Y]EP0119059  (TOSHIBA KK [JP])
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.