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Extract from the Register of European Patents

EP About this file: EP0204300

EP0204300 - A programmable macrocell using EPROM or EEPROM transistors for architecture control in programmable logic circuits [Right-click to bookmark this link]
StatusOpposition rejected
Status updated on  30.08.1996
Database last updated on 31.08.2024
Most recent event   Tooltip22.08.2008Change - opposition data/opponents data or that of the opponents representativepublished on 24.09.2008  [2008/39]
Applicant(s)For all designated states
ALTERA CORPORATION
3525 Monroe Street
Santa Clara, CA 95051 / US
[1986/50]
Inventor(s)01 / Hartman, Robert F.
1231 Regency Place
San Jose, CA 95129 / US
02 / Chan, Yiu-Fai
21396 Maria Lane
Saratoga, CA 95070 / US
03 / Frankovich, Robert J.
1392 South Stelling Road
Cupertino, CA 95014 / US
04 / Ou, Jung-Shing
863 W. California Avenue, No. M
Sunnyvale, CA 94086 / US
05 / So, Hock Chuen
16 Lonetree Court
Milpitas, CA 95035 / US
06 / Wong, Sau-Ching
30 Sugar Hill Drive
Hillsborough, CA 94010 / US
[1986/50]
Representative(s)Meddle, Alan L., et al
FORRESTER & BOEHMERT, Pettenkoferstrasse 20-22
80336 München / DE
[N/P]
Former [1986/50]Meddle, Alan Leonard, et al
FORRESTER & BOEHMERT Franz-Joseph-Strasse 38
D-80801 München / DE
Application number, filing date86107450.802.06.1986
[1986/50]
Priority number, dateUS1985074208906.06.1985         Original published format: US 742089
[1986/50]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0204300
Date:10.12.1986
Language:EN
[1986/50]
Type: A3 Search report 
No.:EP0204300
Date:27.07.1988
Language:EN
[1988/30]
Type: B1 Patent specification 
No.:EP0204300
Date:26.08.1992
Language:EN
[1992/35]
Search report(s)(Supplementary) European search report - dispatched on:EP06.06.1988
ClassificationIPC:H03K19/173, H03K19/177
[1986/50]
CPC:
H03K19/1736 (EP,US); H03K17/693 (EP,US); H03K19/1737 (EP,US)
Designated contracting statesAT,   BE,   CH,   DE,   FR,   GB,   IT,   LI,   LU,   NL,   SE [1986/50]
TitleGerman:Programmierbare Makrozelle mit EPROM- oder EEPROM-Transistoren zur Steuerung der Architektur in programmierbaren logischen Schaltungen[1986/50]
English:A programmable macrocell using EPROM or EEPROM transistors for architecture control in programmable logic circuits[1986/50]
French:Macrocellule programmable utilisant des transistors de EPROM ou EEPROM pour déterminer la configuration de circuits logiques programmables[1986/50]
Examination procedure20.01.1989Examination requested  [1989/13]
15.12.1989Despatch of a communication from the examining division (Time limit: M06)
13.06.1990Reply to a communication from the examining division
27.09.1990Despatch of a communication from the examining division (Time limit: M06)
08.04.1991Reply to a communication from the examining division
13.11.1991Despatch of communication of intention to grant (Approval: Yes)
27.01.1992Communication of intention to grant the patent
23.03.1992Fee for grant paid
23.03.1992Fee for publishing/printing paid
Opposition(s)Opponent(s)01  25.05.1993  08.06.1993  ADMISSIBLE
Koninklijke Philips Electronics N.V.
Groenewoudseweg 1
5621 BA Eindhoven / NL
Opponent's representative
Faessen, Louis Marie Hubertus
Philips
Intellectual Property & Standards
P.O. Box 220
5600 AE Eindhoven / NL
 [N/P]
Former [2008/39]
Opponent(s)01  25.05.1993  08.06.1993  ADMISSIBLE
Koninklijke Philips Electronics N.V.
Groenewoudseweg 1
5621 BA Eindhoven / NL
Opponent's representative
Faessen, Louis Marie Hubertus
Philips Intellectual Property & Standards P.O. Box 220
5600 AE Eindhoven / NL
Former [1993/30]
Opponent(s)01  25.05.1993  08.06.1993  ADMISSIBLE
Philips Electronics N.V.
Groenewoudseweg 1
NL-5621 BA EINDHOVEN / NL
Opponent's representative
Faessen, Louis Marie Hubertus
INTERNATIONAAL OCTROOIBUREAU B.V., Prof. Holstlaan 6
NL-5656 AA Eindhoven / NL
06.09.1993Invitation to proprietor to file observations on the notice of opposition
16.03.1994Reply of patent proprietor to notice(s) of opposition
09.11.1994Despatch of a communication from the opposition division (Time limit: M04)
19.05.1995Despatch of a communication from the opposition division (Time limit: M02)
12.02.1996Date of oral proceedings
20.05.1996Despatch of minutes of oral proceedings
20.05.1996Date of despatch of rejection of opposition
30.05.1996Legal effect of rejection of opposition [1996/42]
Fees paidRenewal fee
14.06.1988Renewal fee patent year 03
12.06.1989Renewal fee patent year 04
12.06.1990Renewal fee patent year 05
17.06.1991Renewal fee patent year 06
25.06.1992Renewal fee patent year 07
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipAT26.08.1992
BE26.08.1992
CH26.08.1992
LI26.08.1992
NL26.08.1992
SE26.08.1992
LU30.06.1993
FR29.02.1996
[2002/23]
Former [1999/52]AT26.08.1992
BE26.08.1992
CH26.08.1992
LI26.08.1992
NL26.08.1992
LU30.06.1993
FR29.02.1996
Former [1996/42]AT26.08.1992
BE26.08.1992
CH26.08.1992
LI26.08.1992
NL26.08.1992
FR29.02.1996
Former [1993/19]AT26.08.1992
BE26.08.1992
CH26.08.1992
LI26.08.1992
NL26.08.1992
Former [1993/15]AT26.08.1992
CH26.08.1992
LI26.08.1992
NL26.08.1992
Former [1993/10]CH26.08.1992
LI26.08.1992
Documents cited:Search[A]US4247918  (IWAHASHI HIROSHI, et al);
 [Y]US4317110  (HSU SHENG T)
 [X]  - WESCON TECHNICAL PAPERS, 30th October - 2nd November 1984, pages 1-6, Anaheim, California, Los Angeles, US; Y.-F. CHAN: "Programmable logic replaces gate arrays"
 [X]  - ELECTRO AND MINI/MICRO NORTHEAST, New York, 23rd-25th April 1985, pages 1-6, New York, US; S.A. KAZMI: "Implementing custom designs with erasable programmable logic devices"
 [X]  - ELECTRONIC DESIGN, vol. 31, no. 25, December 1983, pages 95-98,100,102, Waseca, MN, Denville, NJ, US; B. KITSON et al.: "Programmable logic chip rivals gate arrays in flexibility"
 [X]  - ELECTRONIC DESIGN, vol. 33, no. 8, April 1985, pages 48,50, Hasbrouck Heights, New Jersey, US; D. BURSKY: "Extra feedback path boosts logic chip's I/O flexibility"
 [Y]  - IEEE TRANSACTIONS ON COMPUTERS, vol. C-30, no. 1, January 1981, pages 79-81, IEEE, New York, US; R.E. SUAREZ et al.: "Design of a dynamically programmable logic gate"
 [A]  - ELECTRONICS, vol. 39, no. 22, 31st October 1966, page 70, New York, US; C.H. McDERMOTT: "Suppressed carrier modulator with noncritical components"
ExaminationUS4422072
 US4488246
 WO8505202
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.